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| author | aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> | 2009-03-09 18:50:53 +0000 |
|---|---|---|
| committer | aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> | 2009-03-09 18:50:53 +0000 |
| commit | d42f183c0452a9c769b91e3911566566724983ff (patch) | |
| tree | 6a6c0ef04844f2a0a6f0542cb7c62554a682c63c /tcg/x86_64 | |
| parent | a1f6684d6576df57175c18bfe3fbf23cb61922ab (diff) | |
| download | qemu-d42f183c0452a9c769b91e3911566566724983ff.tar.gz qemu-d42f183c0452a9c769b91e3911566566724983ff.tar.bz2 qemu-d42f183c0452a9c769b91e3911566566724983ff.zip | |
Implement TCG rotation ops for x86-64
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6795 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'tcg/x86_64')
| -rw-r--r-- | tcg/x86_64/tcg-target.c | 22 | ||||
| -rw-r--r-- | tcg/x86_64/tcg-target.h | 2 |
2 files changed, 22 insertions, 2 deletions
diff --git a/tcg/x86_64/tcg-target.c b/tcg/x86_64/tcg-target.c index 33327d1d11..60968327b3 100644 --- a/tcg/x86_64/tcg-target.c +++ b/tcg/x86_64/tcg-target.c @@ -194,6 +194,8 @@ static inline int tcg_target_const_match(tcg_target_long val, #define ARITH_XOR 6 #define ARITH_CMP 7 +#define SHIFT_ROL 0 +#define SHIFT_ROR 1 #define SHIFT_SHL 4 #define SHIFT_SHR 5 #define SHIFT_SAR 7 @@ -1049,7 +1051,13 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args, case INDEX_op_sar_i32: c = SHIFT_SAR; goto gen_shift32; - + case INDEX_op_rotl_i32: + c = SHIFT_ROL; + goto gen_shift32; + case INDEX_op_rotr_i32: + c = SHIFT_ROR; + goto gen_shift32; + case INDEX_op_shl_i64: c = SHIFT_SHL; gen_shift64: @@ -1070,7 +1078,13 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args, case INDEX_op_sar_i64: c = SHIFT_SAR; goto gen_shift64; - + case INDEX_op_rotl_i64: + c = SHIFT_ROL; + goto gen_shift64; + case INDEX_op_rotr_i64: + c = SHIFT_ROR; + goto gen_shift64; + case INDEX_op_brcond_i32: tcg_out_brcond(s, args[2], args[0], args[1], const_args[1], args[3], 0); @@ -1230,6 +1244,8 @@ static const TCGTargetOpDef x86_64_op_defs[] = { { INDEX_op_shl_i32, { "r", "0", "ci" } }, { INDEX_op_shr_i32, { "r", "0", "ci" } }, { INDEX_op_sar_i32, { "r", "0", "ci" } }, + { INDEX_op_rotl_i32, { "r", "0", "ci" } }, + { INDEX_op_rotr_i32, { "r", "0", "ci" } }, { INDEX_op_brcond_i32, { "r", "ri" } }, @@ -1259,6 +1275,8 @@ static const TCGTargetOpDef x86_64_op_defs[] = { { INDEX_op_shl_i64, { "r", "0", "ci" } }, { INDEX_op_shr_i64, { "r", "0", "ci" } }, { INDEX_op_sar_i64, { "r", "0", "ci" } }, + { INDEX_op_rotl_i64, { "r", "0", "ci" } }, + { INDEX_op_rotr_i64, { "r", "0", "ci" } }, { INDEX_op_brcond_i64, { "r", "re" } }, diff --git a/tcg/x86_64/tcg-target.h b/tcg/x86_64/tcg-target.h index 77d0709d6b..1eadf422f1 100644 --- a/tcg/x86_64/tcg-target.h +++ b/tcg/x86_64/tcg-target.h @@ -65,6 +65,8 @@ enum { #define TCG_TARGET_HAS_ext8s_i64 #define TCG_TARGET_HAS_ext16s_i64 #define TCG_TARGET_HAS_ext32s_i64 +#define TCG_TARGET_HAS_rot_i32 +#define TCG_TARGET_HAS_rot_i64 /* Note: must be synced with dyngen-exec.h */ #define TCG_AREG0 TCG_REG_R14 |