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| author | malc <malc@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-07-26 11:21:03 +0000 |
|---|---|---|
| committer | malc <malc@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-07-26 11:21:03 +0000 |
| commit | c070355d398160b6c1ed7ea22753903e96a298d6 (patch) | |
| tree | e233d57ed1d37e5305c95c3d0d3c5f0cf58e787a /tcg/ppc64 | |
| parent | b01d9fea6c82b08b7687d6d9d9b886555720f6b5 (diff) | |
| download | qemu-c070355d398160b6c1ed7ea22753903e96a298d6.tar.gz qemu-c070355d398160b6c1ed7ea22753903e96a298d6.tar.bz2 qemu-c070355d398160b6c1ed7ea22753903e96a298d6.zip | |
Relax memory operations constraints
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4950 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'tcg/ppc64')
| -rw-r--r-- | tcg/ppc64/tcg-target.c | 22 |
1 files changed, 5 insertions, 17 deletions
diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c index 7fc49ce9e3..9d8364125f 100644 --- a/tcg/ppc64/tcg-target.c +++ b/tcg/ppc64/tcg-target.c @@ -217,24 +217,12 @@ static int target_parse_constraint (TCGArgConstraint *ct, const char **pct_str) tcg_regset_reset_reg (ct->u.regs, TCG_REG_R3); tcg_regset_reset_reg (ct->u.regs, TCG_REG_R4); break; - case 'K': /* qemu_st[8..32] constraint */ + case 'S': /* qemu_st constraint */ ct->ct |= TCG_CT_REG; tcg_regset_set32 (ct->u.regs, 0, 0xffffffff); tcg_regset_reset_reg (ct->u.regs, TCG_REG_R3); tcg_regset_reset_reg (ct->u.regs, TCG_REG_R4); tcg_regset_reset_reg (ct->u.regs, TCG_REG_R5); -#if TARGET_LONG_BITS == 64 - tcg_regset_reset_reg (ct->u.regs, TCG_REG_R6); -#endif - break; - case 'M': /* qemu_st64 constraint */ - ct->ct |= TCG_CT_REG; - tcg_regset_set32 (ct->u.regs, 0, 0xffffffff); - tcg_regset_reset_reg (ct->u.regs, TCG_REG_R3); - tcg_regset_reset_reg (ct->u.regs, TCG_REG_R4); - tcg_regset_reset_reg (ct->u.regs, TCG_REG_R5); - tcg_regset_reset_reg (ct->u.regs, TCG_REG_R6); - tcg_regset_reset_reg (ct->u.regs, TCG_REG_R7); break; default: return -1; @@ -1424,10 +1412,10 @@ static const TCGTargetOpDef ppc_op_defs[] = { { INDEX_op_qemu_ld32s, { "r", "L" } }, { INDEX_op_qemu_ld64, { "r", "L" } }, - { INDEX_op_qemu_st8, { "K", "K" } }, - { INDEX_op_qemu_st16, { "K", "K" } }, - { INDEX_op_qemu_st32, { "K", "K" } }, - { INDEX_op_qemu_st64, { "M", "M", "M" } }, + { INDEX_op_qemu_st8, { "S", "S" } }, + { INDEX_op_qemu_st16, { "S", "S" } }, + { INDEX_op_qemu_st32, { "S", "S" } }, + { INDEX_op_qemu_st64, { "S", "S", "S" } }, { INDEX_op_ext8s_i32, { "r", "r" } }, { INDEX_op_ext16s_i32, { "r", "r" } }, |