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| author | Leonid Bloch <leonid.bloch@ravellosystems.com> | 2015-11-11 15:52:46 +0200 |
|---|---|---|
| committer | Jason Wang <jasowang@redhat.com> | 2015-11-12 15:26:54 +0800 |
| commit | 3b27430177498a1728b6765c70b455900f93d73a (patch) | |
| tree | c5a9e14dbf91d90b0d27f6540deb89a92ec2f8ec /tcg/mips | |
| parent | 4aeea330f022f45d0dabff6090ecbb98755c2116 (diff) | |
| download | qemu-3b27430177498a1728b6765c70b455900f93d73a.tar.gz qemu-3b27430177498a1728b6765c70b455900f93d73a.tar.bz2 qemu-3b27430177498a1728b6765c70b455900f93d73a.zip | |
e1000: Implementing various counters
This implements the following Statistic registers (various counters)
according to Intel's specs:
TSCTC GOTCL GOTCH GORCL GORCH MPRC BPRC RUC ROC
BPTC MPTC PTC... PRC...
PLEASE NOTE: these registers will not be active, nor will migrate, until
a compatibility flag will be set (in the next patch in this series).
Signed-off-by: Leonid Bloch <leonid.bloch@ravellosystems.com>
Signed-off-by: Dmitry Fleytman <dmitry.fleytman@ravellosystems.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
Diffstat (limited to 'tcg/mips')
0 files changed, 0 insertions, 0 deletions