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authoredgar_igl <edgar_igl@c046a42c-6fe2-441c-8c8c-71466251a162>2009-04-03 07:29:38 +0000
committeredgar_igl <edgar_igl@c046a42c-6fe2-441c-8c8c-71466251a162>2009-04-03 07:29:38 +0000
commit3c1adf12350b65197d70c4d2911be4d7440d0cfc (patch)
tree33a8c10d924d9155041c22130e36d00ebf53f7ac /target-sh4
parent8cd6345d00a25ffa8828bce31154c88f76fb7fc6 (diff)
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SH: Add cpu_sh4_is_cached for linux-user.
The entire U0 area is assumed to be cacheable. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6969 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-sh4')
-rw-r--r--target-sh4/helper.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/target-sh4/helper.c b/target-sh4/helper.c
index d2e9b3b894..178bfae99a 100644
--- a/target-sh4/helper.c
+++ b/target-sh4/helper.c
@@ -60,6 +60,12 @@ target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
return addr;
}
+int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
+{
+ /* For user mode, only U0 area is cachable. */
+ return !!(addr & 0x80000000);
+}
+
#else /* !CONFIG_USER_ONLY */
#define MMU_OK 0