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authorbalrog <balrog@c046a42c-6fe2-441c-8c8c-71466251a162>2008-12-07 19:08:45 +0000
committerbalrog <balrog@c046a42c-6fe2-441c-8c8c-71466251a162>2008-12-07 19:08:45 +0000
commit1e5459a3fa01824c18272fb840f43e3c138dee76 (patch)
tree8c5a1686a9ffbc4bd02af2fd43dc960f7fb1acf9 /target-sh4
parentd47ede60933f265e558723096e67734db165bdae (diff)
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SH: On-chip PCI controller support (Takashi YOSHII).
This patch adds SuperH on-chip PCI controller(PCIC) support. Signed-off-by: Takashi YOSHII <takasi-y@ops.dti.ne.jp> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5927 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-sh4')
-rw-r--r--target-sh4/helper.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/target-sh4/helper.c b/target-sh4/helper.c
index c536015cfe..f077462f7d 100644
--- a/target-sh4/helper.c
+++ b/target-sh4/helper.c
@@ -439,6 +439,9 @@ int get_physical_address(CPUState * env, target_ulong * physical,
if (address >= 0x80000000 && address < 0xc0000000) {
/* Mask upper 3 bits for P1 and P2 areas */
*physical = address & 0x1fffffff;
+ } else if (address >= 0xfd000000 && address < 0xfe000000) {
+ /* PCI memory space */
+ *physical = address;
} else if (address >= 0xfc000000) {
/*
* Mask upper 3 bits for control registers in P4 area,