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| author | Richard Henderson <rth@twiddle.net> | 2012-08-22 09:22:23 -0700 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2013-01-05 12:18:38 -0800 |
| commit | a79ba3398a0aa7fdd544ce28d2950b4eeb3c16a5 (patch) | |
| tree | 05bfa7a6e3055fad6bd6d24896b0aa155e155643 /target-s390x | |
| parent | cbe24bfa91d21766f2953c2da92c1e3dd13d8387 (diff) | |
| download | qemu-a79ba3398a0aa7fdd544ce28d2950b4eeb3c16a5.tar.gz qemu-a79ba3398a0aa7fdd544ce28d2950b4eeb3c16a5.tar.bz2 qemu-a79ba3398a0aa7fdd544ce28d2950b4eeb3c16a5.zip | |
target-s390: Convert SHIFT DOUBLE
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target-s390x')
| -rw-r--r-- | target-s390x/insn-data.def | 8 | ||||
| -rw-r--r-- | target-s390x/translate.c | 30 |
2 files changed, 8 insertions, 30 deletions
diff --git a/target-s390x/insn-data.def b/target-s390x/insn-data.def index 6020e04e0b..50a176476c 100644 --- a/target-s390x/insn-data.def +++ b/target-s390x/insn-data.def @@ -335,6 +335,14 @@ C(0x8800, SRL, RS_a, Z, r1_32u, sh32, new, r1_32, srl, 0) C(0xebde, SRLK, RSY_a, DO, r3_32u, sh32, new, r1_32, srl, 0) C(0xeb0c, SRLG, RSY_a, Z, r3_o, sh64, r1, 0, srl, 0) +/* SHIFT LEFT DOUBLE */ + D(0x8f00, SLDA, RS_a, Z, r1_D32, sh64, new, r1_D32, sla, 0, 31) +/* SHIFT LEFT DOUBLE LOGICAL */ + C(0x8d00, SLDL, RS_a, Z, r1_D32, sh64, new, r1_D32, sll, 0) +/* SHIFT RIGHT DOUBLE */ + C(0x8e00, SRDA, RS_a, Z, r1_D32, sh64, new, r1_D32, sra, s64) +/* SHIFT RIGHT DOUBLE LOGICAL */ + C(0x8c00, SRDL, RS_a, Z, r1_D32, sh64, new, r1_D32, srl, 0) /* STORE */ C(0x5000, ST, RX_a, Z, r1_o, a2, 0, 0, st32, 0) diff --git a/target-s390x/translate.c b/target-s390x/translate.c index bb3721d30b..54cd2fa1de 100644 --- a/target-s390x/translate.c +++ b/target-s390x/translate.c @@ -2288,36 +2288,6 @@ static void disas_s390_insn(CPUS390XState *env, DisasContext *s) LOG_DISAS("opc 0x%x\n", opc); switch (opc) { - case 0x8c: /* SRDL R1,D2(B2) [RS] */ - case 0x8d: /* SLDL R1,D2(B2) [RS] */ - case 0x8e: /* SRDA R1,D2(B2) [RS] */ - insn = ld_code4(env, s->pc); - decode_rs(s, insn, &r1, &r3, &b2, &d2); - tmp = get_address(s, 0, b2, d2); /* shift */ - tmp2 = tcg_temp_new_i64(); - tmp32_1 = load_reg32(r1); - tmp32_2 = load_reg32(r1 + 1); - tcg_gen_concat_i32_i64(tmp2, tmp32_2, tmp32_1); /* operand */ - switch (opc) { - case 0x8c: - tcg_gen_shr_i64(tmp2, tmp2, tmp); - break; - case 0x8d: - tcg_gen_shl_i64(tmp2, tmp2, tmp); - break; - case 0x8e: - tcg_gen_sar_i64(tmp2, tmp2, tmp); - set_cc_s64(s, tmp2); - break; - } - tcg_gen_shri_i64(tmp, tmp2, 32); - tcg_gen_trunc_i64_i32(tmp32_1, tmp); - store_reg32(r1, tmp32_1); - tcg_gen_trunc_i64_i32(tmp32_2, tmp2); - store_reg32(r1 + 1, tmp32_2); - tcg_temp_free_i64(tmp); - tcg_temp_free_i64(tmp2); - break; case 0x98: /* LM R1,R3,D2(B2) [RS] */ case 0x90: /* STM R1,R3,D2(B2) [RS] */ insn = ld_code4(env, s->pc); |