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| author | Alexander Graf <agraf@suse.de> | 2012-02-21 19:41:59 +0100 |
|---|---|---|
| committer | Andreas Färber <afaerber@suse.de> | 2012-03-14 22:20:24 +0100 |
| commit | fc0b2c0f1a8eb679d28763832f3223259bf37b34 (patch) | |
| tree | 405c22ba39983f138505e7da42be118019dd9acb /target-ppc | |
| parent | 418ba9e5d6849ef2e8512d8853628ce4bf37937a (diff) | |
| download | qemu-fc0b2c0f1a8eb679d28763832f3223259bf37b34.tar.gz qemu-fc0b2c0f1a8eb679d28763832f3223259bf37b34.tar.bz2 qemu-fc0b2c0f1a8eb679d28763832f3223259bf37b34.zip | |
PPC: 405: Use proper CPU reset
On ppc405ep there is a register that allows for software to reset the
core, but not the whole system. Implement this reset using a reset
interrupt.
This gets rid of a bunch of #if 0'ed code.
Reported-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Diffstat (limited to 'target-ppc')
| -rw-r--r-- | target-ppc/cpu.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index fbcf4881a8..ac753f3a06 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -2051,6 +2051,9 @@ enum { PPC_INTERRUPT_PERFM, /* Performance monitor interrupt */ }; +/* CPU should be reset next, restart from scratch afterwards */ +#define CPU_INTERRUPT_RESET CPU_INTERRUPT_TGT_INT_0 + /*****************************************************************************/ static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, |