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| author | Tom Musta <tommusta@gmail.com> | 2014-03-31 16:04:01 -0500 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2014-04-08 11:20:03 +0200 |
| commit | 6bbad7a91efe49b080391a45bc6305449050465a (patch) | |
| tree | 1154149899ea9d5e7fff4684dec7bf34df78155e /target-ppc | |
| parent | 50fc89e7b1a2837a2d92025aa2ed161d8439743b (diff) | |
| download | qemu-6bbad7a91efe49b080391a45bc6305449050465a.tar.gz qemu-6bbad7a91efe49b080391a45bc6305449050465a.tar.bz2 qemu-6bbad7a91efe49b080391a45bc6305449050465a.zip | |
target-ppc: Correct VSX FP to FP Conversions
This change corrects the VSX double precision to single precision and
single precision to double precisions conversion routines. The endian
correct accessors are now used. The auxiliary "j" index is no longer
necessary and is eliminated.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Tested-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'target-ppc')
| -rw-r--r-- | target-ppc/fpu_helper.c | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c index 6233d5eb18..12bec903b9 100644 --- a/target-ppc/fpu_helper.c +++ b/target-ppc/fpu_helper.c @@ -2512,7 +2512,6 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ getVSR(xT(opcode), &xt, env); \ \ for (i = 0; i < nels; i++) { \ - int j = 2*i + JOFFSET; \ xt.tfld = stp##_to_##ttp(xb.sfld, &env->fp_status); \ if (unlikely(stp##_is_signaling_nan(xb.sfld))) { \ fload_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \ @@ -2528,10 +2527,10 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ helper_float_check_status(env); \ } -VSX_CVT_FP_TO_FP(xscvdpsp, 1, float64, float32, f64[i], f32[j], 1) -VSX_CVT_FP_TO_FP(xscvspdp, 1, float32, float64, f32[j], f64[i], 1) -VSX_CVT_FP_TO_FP(xvcvdpsp, 2, float64, float32, f64[i], f32[j], 0) -VSX_CVT_FP_TO_FP(xvcvspdp, 2, float32, float64, f32[j], f64[i], 0) +VSX_CVT_FP_TO_FP(xscvdpsp, 1, float64, float32, VsrD(0), VsrW(0), 1) +VSX_CVT_FP_TO_FP(xscvspdp, 1, float32, float64, VsrW(0), VsrD(0), 1) +VSX_CVT_FP_TO_FP(xvcvdpsp, 2, float64, float32, VsrD(i), VsrW(2*i), 0) +VSX_CVT_FP_TO_FP(xvcvspdp, 2, float32, float64, VsrW(2*i), VsrD(i), 0) uint64_t helper_xscvdpspn(CPUPPCState *env, uint64_t xb) { |