diff options
| author | Aurelien Jarno <aurelien@aurel32.net> | 2009-09-28 23:40:59 +0200 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2009-09-30 23:12:51 +0200 |
| commit | 941694d09aa158ff18bc1f12e569293e55217995 (patch) | |
| tree | 2126af76a327555f23111ff9e406b47accdbd14e /target-mips | |
| parent | cc739bb0c4d86554da10e029beebc5d98bd066dc (diff) | |
| download | qemu-941694d09aa158ff18bc1f12e569293e55217995.tar.gz qemu-941694d09aa158ff18bc1f12e569293e55217995.tar.bz2 qemu-941694d09aa158ff18bc1f12e569293e55217995.zip | |
target-mips: make sure constants are in the second argument
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-mips')
| -rw-r--r-- | target-mips/translate.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/target-mips/translate.c b/target-mips/translate.c index a8e8ae3633..58f483fa0a 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -803,9 +803,9 @@ generate_exception (DisasContext *ctx, int excp) } /* Addresses computation */ -static inline void gen_op_addr_add (DisasContext *ctx, TCGv t0, TCGv t1) +static inline void gen_op_addr_add (DisasContext *ctx, TCGv ret, TCGv arg0, TCGv arg1) { - tcg_gen_add_tl(t0, t0, t1); + tcg_gen_add_tl(ret, arg0, arg1); #if defined(TARGET_MIPS64) /* For compatibility with 32-bit code, data reference in user mode @@ -813,7 +813,7 @@ static inline void gen_op_addr_add (DisasContext *ctx, TCGv t0, TCGv t1) See the MIPS64 PRA manual, section 4.10. */ if (((ctx->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) && !(ctx->hflags & MIPS_HFLAG_UX)) { - tcg_gen_ext32s_i64(t0, t0); + tcg_gen_ext32s_i64(ret, ret); } #endif } @@ -1005,7 +1005,7 @@ static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt, gen_load_gpr(t0, base); } else { tcg_gen_movi_tl(t0, offset); - gen_op_addr_add(ctx, t0, cpu_gpr[base]); + gen_op_addr_add(ctx, t0, cpu_gpr[base], t0); } /* Don't do NOP if destination is zero: we must perform the actual memory access. */ @@ -1163,7 +1163,7 @@ static void gen_st_cond (DisasContext *ctx, uint32_t opc, int rt, gen_load_gpr(t0, base); } else { tcg_gen_movi_tl(t0, offset); - gen_op_addr_add(ctx, t0, cpu_gpr[base]); + gen_op_addr_add(ctx, t0, cpu_gpr[base], t0); } /* Don't do NOP if destination is zero: we must perform the actual memory access. */ @@ -1202,7 +1202,7 @@ static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft, gen_load_gpr(t0, base); } else { tcg_gen_movi_tl(t0, offset); - gen_op_addr_add(ctx, t0, cpu_gpr[base]); + gen_op_addr_add(ctx, t0, cpu_gpr[base], t0); } /* Don't do NOP if destination is zero: we must perform the actual memory access. */ @@ -7264,7 +7264,7 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc, gen_load_gpr(t0, base); } else { gen_load_gpr(t0, index); - gen_op_addr_add(ctx, t0, cpu_gpr[base]); + gen_op_addr_add(ctx, t0, cpu_gpr[base], t0); } /* Don't do NOP if destination is zero: we must perform the actual memory access. */ |