diff options
| author | Aurelien Jarno <aurelien@aurel32.net> | 2010-06-30 20:00:31 +0200 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2010-06-30 20:00:31 +0200 |
| commit | 6fbab869257a87d9d80dec1a094827952448f27f (patch) | |
| tree | 495217b31afe037321482ccdd27ff68822623700 /target-mips | |
| parent | 33dd298323c36ec2de7a21b85d29bfd9ba255d72 (diff) | |
| download | qemu-6fbab869257a87d9d80dec1a094827952448f27f.tar.gz qemu-6fbab869257a87d9d80dec1a094827952448f27f.tar.bz2 qemu-6fbab869257a87d9d80dec1a094827952448f27f.zip | |
target-mips: fix DINSU instruction
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-mips')
| -rw-r--r-- | target-mips/translate.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target-mips/translate.c b/target-mips/translate.c index 8531d6cc12..804b6e4bc4 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -2764,7 +2764,7 @@ static void gen_bitops (DisasContext *ctx, uint32_t opc, int rt, case OPC_DINSU: if (lsb > msb) goto fail; - mask = ((1ULL << (msb - lsb + 1)) - 1) << lsb; + mask = ((1ULL << (msb - lsb + 1)) - 1) << (lsb + 32); gen_load_gpr(t0, rt); tcg_gen_andi_tl(t0, t0, ~mask); tcg_gen_shli_tl(t1, t1, lsb + 32); |