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| author | Alistair Francis <alistair.francis@xilinx.com> | 2014-01-13 13:35:26 +1000 |
|---|---|---|
| committer | Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 2014-01-14 11:08:36 +1000 |
| commit | 73c694565c6144e0c4e15041b5250a04a25107c3 (patch) | |
| tree | a8ea3af63195bd6e0f183d6bc3f7e15393d35935 /target-microblaze | |
| parent | 83e6813a93e38976391b8c382c3375e3e188df3e (diff) | |
| download | qemu-73c694565c6144e0c4e15041b5250a04a25107c3.tar.gz qemu-73c694565c6144e0c4e15041b5250a04a25107c3.tar.bz2 qemu-73c694565c6144e0c4e15041b5250a04a25107c3.zip | |
Microblaze: Convert Microblaze-pic handling to GPIOs
This patch uses inbound GPIO lines (IRQ and FIR) for
interrupts instead of using the old pic_cpu method,
which doesn't correspond to real hardware.
This creates the CPU's inbound IRQ and FIR GPIO lines and
updates the Microblaze boards to use this new method.
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Suggested-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reveiwed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Diffstat (limited to 'target-microblaze')
| -rw-r--r-- | target-microblaze/cpu.c | 21 | ||||
| -rw-r--r-- | target-microblaze/cpu.h | 4 |
2 files changed, 25 insertions, 0 deletions
diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c index 0ef9aa4b74..f108c0b521 100644 --- a/target-microblaze/cpu.c +++ b/target-microblaze/cpu.c @@ -4,6 +4,7 @@ * Copyright (c) 2009 Edgar E. Iglesias * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd. * Copyright (c) 2012 SUSE LINUX Products GmbH + * Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB. * * This library is free software; you can redistribute it and/or * modify it under the terms of the GNU Lesser General Public @@ -33,6 +34,21 @@ static void mb_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.sregs[SR_PC] = value; } +#ifndef CONFIG_USER_ONLY +static void microblaze_cpu_set_irq(void *opaque, int irq, int level) +{ + MicroBlazeCPU *cpu = opaque; + CPUState *cs = CPU(cpu); + int type = irq ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD; + + if (level) { + cpu_interrupt(cs, type); + } else { + cpu_reset_interrupt(cs, type); + } +} +#endif + /* CPUClass::reset() */ static void mb_cpu_reset(CPUState *s) { @@ -111,6 +127,11 @@ static void mb_cpu_initfn(Object *obj) set_float_rounding_mode(float_round_nearest_even, &env->fp_status); +#ifndef CONFIG_USER_ONLY + /* Inbound IRQ and FIR lines */ + qdev_init_gpio_in(DEVICE(cpu), microblaze_cpu_set_irq, 2); +#endif + if (tcg_enabled() && !tcg_initialized) { tcg_initialized = true; mb_tcg_init(); diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h index e1415f043c..1df014e92e 100644 --- a/target-microblaze/cpu.h +++ b/target-microblaze/cpu.h @@ -48,6 +48,10 @@ typedef struct CPUMBState CPUMBState; /* MicroBlaze-specific interrupt pending bits. */ #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 +/* Meanings of the MBCPU object's two inbound GPIO lines */ +#define MB_CPU_IRQ 0 +#define MB_CPU_FIR 1 + /* Register aliases. R0 - R15 */ #define R_SP 1 #define SR_PC 0 |