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authorAurelien Jarno <aurelien@aurel32.net>2013-03-26 19:56:01 +0100
committerAurelien Jarno <aurelien@aurel32.net>2013-04-01 18:49:15 +0200
commit34c6addd4b22583e7b408c0d1452eab753cbfb62 (patch)
treedaf40c5d89fcfd7e8e77d3d1ae4082021adad3cb /target-i386
parentc7b4c36714a442ae5abd26de293cb5e967be6e12 (diff)
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target-i386: SSE4.1: fix pinsrb instruction
gen_op_mov_TN_reg() loads the value in cpu_T[0], so this temporary should be used instead of cpu_tmp0. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'target-i386')
-rw-r--r--target-i386/translate.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 7239696be6..7596a90dc4 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -4404,9 +4404,9 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
if (mod == 3)
gen_op_mov_TN_reg(OT_LONG, 0, rm);
else
- tcg_gen_qemu_ld8u(cpu_tmp0, cpu_A0,
+ tcg_gen_qemu_ld8u(cpu_T[0], cpu_A0,
(s->mem_index >> 2) - 1);
- tcg_gen_st8_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State,
+ tcg_gen_st8_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
xmm_regs[reg].XMM_B(val & 15)));
break;
case 0x21: /* insertps */