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| author | Richard Henderson <rth@twiddle.net> | 2013-01-23 13:33:59 -0800 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2013-02-18 15:03:57 -0800 |
| commit | 086c40778485f9a52d41a66fd4ef0d8723a2ac0a (patch) | |
| tree | 3f77bb7822b3cc5027b9f849ba10fecd9512d9d9 /target-i386/translate.c | |
| parent | b666265b2071e4288110f6553b598efe00246d06 (diff) | |
| download | qemu-086c40778485f9a52d41a66fd4ef0d8723a2ac0a.tar.gz qemu-086c40778485f9a52d41a66fd4ef0d8723a2ac0a.tar.bz2 qemu-086c40778485f9a52d41a66fd4ef0d8723a2ac0a.zip | |
target-i386: do not call helper to compute ZF/SF
ZF, SF and PF can always be computed from CC_DST except in the
CC_OP_EFLAGS case (and CC_OP_DYNAMIC, which just resolves to CC_OP_EFLAGS
in gen_compute_eflags). Use setcond to compute ZF and SF.
We could also use a table lookup to compute PF.
Reviewed-by: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target-i386/translate.c')
| -rw-r--r-- | target-i386/translate.c | 37 |
1 files changed, 31 insertions, 6 deletions
diff --git a/target-i386/translate.c b/target-i386/translate.c index a767b50b57..026fbd6852 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -900,9 +900,22 @@ static void gen_compute_eflags_p(DisasContext *s, TCGv reg) /* compute eflags.S to reg */ static void gen_compute_eflags_s(DisasContext *s, TCGv reg) { - gen_compute_eflags(s); - tcg_gen_shri_tl(reg, cpu_cc_src, 7); - tcg_gen_andi_tl(reg, reg, 1); + switch (s->cc_op) { + case CC_OP_DYNAMIC: + gen_compute_eflags(s); + /* FALLTHRU */ + case CC_OP_EFLAGS: + tcg_gen_shri_tl(reg, cpu_cc_src, 7); + tcg_gen_andi_tl(reg, reg, 1); + break; + default: + { + int size = (s->cc_op - CC_OP_ADDB) & 3; + TCGv t0 = gen_ext_tl(reg, cpu_cc_dst, size, true); + tcg_gen_setcondi_tl(TCG_COND_LT, reg, t0, 0); + } + break; + } } /* compute eflags.O to reg */ @@ -916,9 +929,21 @@ static void gen_compute_eflags_o(DisasContext *s, TCGv reg) /* compute eflags.Z to reg */ static void gen_compute_eflags_z(DisasContext *s, TCGv reg) { - gen_compute_eflags(s); - tcg_gen_shri_tl(reg, cpu_cc_src, 6); - tcg_gen_andi_tl(reg, reg, 1); + switch (s->cc_op) { + case CC_OP_DYNAMIC: + gen_compute_eflags(s); + /* FALLTHRU */ + case CC_OP_EFLAGS: + tcg_gen_shri_tl(reg, cpu_cc_src, 6); + tcg_gen_andi_tl(reg, reg, 1); + break; + default: + { + int size = (s->cc_op - CC_OP_ADDB) & 3; + TCGv t0 = gen_ext_tl(reg, cpu_cc_dst, size, false); + tcg_gen_setcondi_tl(TCG_COND_EQ, reg, t0, 0); + } + } } static inline void gen_setcc_slow_T0(DisasContext *s, int jcc_op) |