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| author | Edgar E. Iglesias <edgar.iglesias@gmail.com> | 2010-07-05 11:39:04 +0200 |
|---|---|---|
| committer | Edgar E. Iglesias <edgar.iglesias@gmail.com> | 2010-07-05 11:39:04 +0200 |
| commit | 9f5a1fae7ee1a7c66462e5b8e9d21552d4dc5027 (patch) | |
| tree | a4f19996d46a0fdeea5b9387bcf7df39332ca08a /target-cris/mmu.c | |
| parent | 3c4fe427edc88b04bd528351f5ce1c8a2e14f5f8 (diff) | |
| download | qemu-9f5a1fae7ee1a7c66462e5b8e9d21552d4dc5027.tar.gz qemu-9f5a1fae7ee1a7c66462e5b8e9d21552d4dc5027.tar.bz2 qemu-9f5a1fae7ee1a7c66462e5b8e9d21552d4dc5027.zip | |
cris: Avoid debug clobbering for both I & D MMU state.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@axis.com>
Diffstat (limited to 'target-cris/mmu.c')
| -rw-r--r-- | target-cris/mmu.c | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/target-cris/mmu.c b/target-cris/mmu.c index 07967dddb0..773438e9f4 100644 --- a/target-cris/mmu.c +++ b/target-cris/mmu.c @@ -135,7 +135,7 @@ static void dump_tlb(CPUState *env, int mmu) /* rw 0 = read, 1 = write, 2 = exec. */ static int cris_mmu_translate_page(struct cris_mmu_result *res, CPUState *env, uint32_t vaddr, - int rw, int usermode) + int rw, int usermode, int debug) { unsigned int vpage; unsigned int idx; @@ -261,7 +261,7 @@ static int cris_mmu_translate_page(struct cris_mmu_result *res, set = env->mmu_rand_lfsr & 3; } - if (!match) { + if (!match && !debug) { cris_mmu_update_rand_lfsr(env); /* Compute index. */ @@ -330,7 +330,7 @@ void cris_mmu_flush_pid(CPUState *env, uint32_t pid) int cris_mmu_translate(struct cris_mmu_result *res, CPUState *env, uint32_t vaddr, - int rw, int mmu_idx) + int rw, int mmu_idx, int debug) { int seg; int miss = 0; @@ -357,9 +357,10 @@ int cris_mmu_translate(struct cris_mmu_result *res, base = cris_mmu_translate_seg(env, seg); res->phy = base | (0x0fffffff & vaddr); res->prot = PAGE_BITS; + } else { + miss = cris_mmu_translate_page(res, env, vaddr, rw, + is_user, debug); } - else - miss = cris_mmu_translate_page(res, env, vaddr, rw, is_user); done: env->pregs[PR_SRS] = old_srs; return miss; |