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authorAndreas Färber <afaerber@suse.de>2013-06-29 18:55:54 +0200
committerAndreas Färber <afaerber@suse.de>2013-07-23 02:41:33 +0200
commit00b941e581b5c42645f836ef530705bb76a3e6bb (patch)
tree4c291f0999809416681f06f575b8ec1288744c2d /target-cris/helper.c
parent385b9f0e4d8c60037c937edd7a3735fff7570429 (diff)
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cpu: Turn cpu_get_phys_page_debug() into a CPUClass hook
Change breakpoint_invalidate() argument to CPUState alongside. Since all targets now assign a softmmu-only field, we can drop helpers cpu_class_set_{do_unassigned_access,vmsd}() and device_class_set_vmsd(). Prepares for changing cpu_memory_rw_debug() argument to CPUState. Acked-by: Max Filippov <jcmvbkbc@gmail.com> (for xtensa) Signed-off-by: Andreas Färber <afaerber@suse.de>
Diffstat (limited to 'target-cris/helper.c')
-rw-r--r--target-cris/helper.c7
1 files changed, 4 insertions, 3 deletions
diff --git a/target-cris/helper.c b/target-cris/helper.c
index aba7537265..d274b388b8 100644
--- a/target-cris/helper.c
+++ b/target-cris/helper.c
@@ -255,16 +255,17 @@ void cris_cpu_do_interrupt(CPUState *cs)
env->pregs[PR_ERP]);
}
-hwaddr cpu_get_phys_page_debug(CPUCRISState * env, target_ulong addr)
+hwaddr cris_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
{
+ CRISCPU *cpu = CRIS_CPU(cs);
uint32_t phy = addr;
struct cris_mmu_result res;
int miss;
- miss = cris_mmu_translate(&res, env, addr, 0, 0, 1);
+ miss = cris_mmu_translate(&res, &cpu->env, addr, 0, 0, 1);
/* If D TLB misses, try I TLB. */
if (miss) {
- miss = cris_mmu_translate(&res, env, addr, 2, 0, 1);
+ miss = cris_mmu_translate(&res, &cpu->env, addr, 2, 0, 1);
}
if (!miss) {