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authorEdgar E. Iglesias <edgar.iglesias@xilinx.com>2014-05-27 17:09:52 +0100
committerPeter Maydell <peter.maydell@linaro.org>2014-05-27 17:09:52 +0100
commit2a923c4dde779fc3e5a55886bfa4085e590cbc96 (patch)
tree89711b255a7ea964f4d0699f358ce7c5a0d09f94 /target-arm/internals.h
parent28c9457df08755ef7d98eb58b17e0e0898553b41 (diff)
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target-arm: A64: Introduce aarch64_banked_spsr_index()
Add aarch64_banked_spsr_index(), used to map an Exception Level to an index in the banked_spsr array. Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1400980132-25949-13-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm/internals.h')
-rw-r--r--target-arm/internals.h14
1 files changed, 14 insertions, 0 deletions
diff --git a/target-arm/internals.h b/target-arm/internals.h
index d63a975a7e..c9897c2cba 100644
--- a/target-arm/internals.h
+++ b/target-arm/internals.h
@@ -75,6 +75,20 @@ static inline void arm_log_exception(int idx)
*/
#define GTIMER_SCALE 16
+/*
+ * For AArch64, map a given EL to an index in the banked_spsr array.
+ */
+static inline unsigned int aarch64_banked_spsr_index(unsigned int el)
+{
+ static const unsigned int map[4] = {
+ [1] = 0, /* EL1. */
+ [2] = 6, /* EL2. */
+ [3] = 7, /* EL3. */
+ };
+ assert(el >= 1 && el <= 3);
+ return map[el];
+}
+
int bank_number(int mode);
void switch_mode(CPUARMState *, int);
void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu);