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| author | Nicholas Piggin <npiggin@gmail.com> | 2016-10-20 17:59:10 +1100 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2016-10-28 09:36:58 +1100 |
| commit | f85bcec31ee578eccf6182be158d6ac6d9b90a4c (patch) | |
| tree | 567e904942415e82c526d49bb4cfffbb30d86cba /include/hw/ppc | |
| parent | e3403258a20c61859ca1917bb86bc206e5846784 (diff) | |
| download | qemu-f85bcec31ee578eccf6182be158d6ac6d9b90a4c.tar.gz qemu-f85bcec31ee578eccf6182be158d6ac6d9b90a4c.tar.bz2 qemu-f85bcec31ee578eccf6182be158d6ac6d9b90a4c.zip | |
ppc: fix MSR_ME handling for system reset interrupt
Power ISA specifies ME bit handling for system reset interrupt:
if the interrupt occurred while the thread was in power-saving
mode, set to 1; otherwise not altered
Power ISA 3.0, section 6.5 "Interrupt Definitions", Figure 64.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Greg Kurz <groug@kaod.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'include/hw/ppc')
0 files changed, 0 insertions, 0 deletions