diff options
author | David Gibson <david@gibson.dropbear.id.au> | 2012-03-07 15:12:21 +0000 |
---|---|---|
committer | Alexander Graf <agraf@suse.de> | 2012-03-15 13:12:12 +0100 |
commit | d07fee7e8ad9d3611404fa145270d3b885b2772a (patch) | |
tree | 0612fa251e7e968bbd5558575e17678ed70d12df /hw/spapr_vio.c | |
parent | eb6ea4b22e89d4c6ed510c7cfcd33d15be92733b (diff) | |
download | qemu-d07fee7e8ad9d3611404fa145270d3b885b2772a.tar.gz qemu-d07fee7e8ad9d3611404fa145270d3b885b2772a.tar.bz2 qemu-d07fee7e8ad9d3611404fa145270d3b885b2772a.zip |
pseries: Add support for level interrupts to XICS
The pseries "xics" interrupt controller, like most interrupt
controllers can support both message (i.e. edge sensitive) interrupts
and level sensitive interrupts, but it needs to know which are which.
When I implemented the xics emulation for qemu, the only devices we
supported were the PAPR virtual IO devices. These devices only use
message interrupts, so they were the only ones I implemented in xics.
Since then, however, we have added support for PCI devices, which use
level sensitive interrupts. It turns out the message interrupt logic
still actually works most of the time for these, but there are
circumstances where we can lost interrupts due to the incorrect
interrupt logic.
This patch, therefore, implements the correct xics level-sensitive
interrupt logic. The type of the interrupt is set when a device
allocates a new xics interrupt.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'hw/spapr_vio.c')
-rw-r--r-- | hw/spapr_vio.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/spapr_vio.c b/hw/spapr_vio.c index 2fb3cee266..dbf5a9017e 100644 --- a/hw/spapr_vio.c +++ b/hw/spapr_vio.c @@ -670,7 +670,7 @@ static int spapr_vio_busdev_init(DeviceState *qdev) dev->qdev.id = id; } - dev->qirq = spapr_allocate_irq(dev->vio_irq_num, &dev->vio_irq_num); + dev->qirq = spapr_allocate_msi(dev->vio_irq_num, &dev->vio_irq_num); if (!dev->qirq) { return -1; } |