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authoraliguori <aliguori@c046a42c-6fe2-441c-8c8c-71466251a162>2009-01-26 15:37:35 +0000
committeraliguori <aliguori@c046a42c-6fe2-441c-8c8c-71466251a162>2009-01-26 15:37:35 +0000
commitdeb54399df163e782aff00beb106f3b6a7cc9663 (patch)
tree00f99dbd1adbf0f2c7ac75befc848a454c77aefa /hw/ppc4xx_pci.c
parent90a1e3c0b5811d6b334085d56fba1f5f47eaaea3 (diff)
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Define PCI vendor and device IDs in pci.h (Stuart Brady)
This patch defines PCI vendor and device IDs in pci.h (matching those from Linux's pci_ids.h), and uses those definitions where appropriate. Change from v1: Introduces pci_config_set_vendor_id() / pci_config_set_device_id() accessors as suggested by Anthony Liguori. Signed-off-by: Stuart Brady <stuart.brady@gmail.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6442 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'hw/ppc4xx_pci.c')
-rw-r--r--hw/ppc4xx_pci.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/hw/ppc4xx_pci.c b/hw/ppc4xx_pci.c
index b21c2feff2..7d40b91a48 100644
--- a/hw/ppc4xx_pci.c
+++ b/hw/ppc4xx_pci.c
@@ -366,6 +366,7 @@ PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4],
PPC4xxPCIState *controller;
int index;
static int ppc4xx_pci_id;
+ uint8_t *pci_conf;
controller = qemu_mallocz(sizeof(PPC4xxPCIState));
if (!controller)
@@ -378,12 +379,11 @@ PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4],
controller->pci_dev = pci_register_device(controller->pci_state.bus,
"host bridge", sizeof(PCIDevice),
0, NULL, NULL);
- controller->pci_dev->config[0x00] = 0x14; // vendor_id
- controller->pci_dev->config[0x01] = 0x10;
- controller->pci_dev->config[0x02] = 0x7f; // device_id
- controller->pci_dev->config[0x03] = 0x02;
- controller->pci_dev->config[0x0a] = 0x80; // class_sub = other bridge type
- controller->pci_dev->config[0x0b] = 0x06; // class_base = PCI_bridge
+ pci_conf = controller->pci_dev->config;
+ pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_IBM);
+ pci_config_set_device_id(pci_conf, 0x027f); // device_id
+ pci_conf[0x0a] = 0x80; // class_sub = other bridge type
+ pci_conf[0x0b] = 0x06; // class_base = PCI_bridge
/* CFGADDR */
index = cpu_register_io_memory(0, pci4xx_cfgaddr_read,