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authorAlexey Kardashevskiy <aik@ozlabs.ru>2013-09-26 16:18:48 +1000
committerAlexander Graf <agraf@suse.de>2013-10-25 23:25:47 +0200
commit5cc7a967e9de8c7b16c15aee4cb9f5bfcf0c5989 (patch)
tree2a685a99e349179e7a777366fc4ad9ace414e6c9 /hw/ppc/spapr_pci.c
parent9554233c9b8fe7d94dfa53db09ce3d186f2e8b9e (diff)
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spapr-pci: enable irqfd for INTx
This enables IRQFD for LSI (level triggered INTx interrupts) by adding a spapr_route_intx_pin_to_irq() callback to the sPAPR PCI host bus. This callback is called to know the global interrupt number to link resampling fd with IRQFD's fd in KVM. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'hw/ppc/spapr_pci.c')
-rw-r--r--hw/ppc/spapr_pci.c13
1 files changed, 13 insertions, 0 deletions
diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c
index 9b6ee32acf..edb4cb0413 100644
--- a/hw/ppc/spapr_pci.c
+++ b/hw/ppc/spapr_pci.c
@@ -432,6 +432,17 @@ static void pci_spapr_set_irq(void *opaque, int irq_num, int level)
qemu_set_irq(spapr_phb_lsi_qirq(phb, irq_num), level);
}
+static PCIINTxRoute spapr_route_intx_pin_to_irq(void *opaque, int pin)
+{
+ sPAPRPHBState *sphb = SPAPR_PCI_HOST_BRIDGE(opaque);
+ PCIINTxRoute route;
+
+ route.mode = PCI_INTX_ENABLED;
+ route.irq = sphb->lsi_table[pin].irq;
+
+ return route;
+}
+
/*
* MSI/MSIX memory region implementation.
* The handler handles both MSI and MSIX.
@@ -610,6 +621,8 @@ static int spapr_phb_init(SysBusDevice *s)
pci_setup_iommu(bus, spapr_pci_dma_iommu, sphb);
+ pci_bus_set_route_irq_fn(bus, spapr_route_intx_pin_to_irq);
+
QLIST_INSERT_HEAD(&spapr->phbs, sphb, list);
/* Initialize the LSI table */