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author | aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-12-18 22:43:40 +0000 |
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committer | aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-12-18 22:43:40 +0000 |
commit | 7f0210c60758c7b71b7264e8bd5f2f3a54ff59d6 (patch) | |
tree | 6ecdf4863bec8c4d42d8f259239afb6d70a90829 /hw/pci.h | |
parent | 4ee259909d7da93a76cd286d866624cca8f81b85 (diff) | |
download | qemu-7f0210c60758c7b71b7264e8bd5f2f3a54ff59d6.tar.gz qemu-7f0210c60758c7b71b7264e8bd5f2f3a54ff59d6.tar.bz2 qemu-7f0210c60758c7b71b7264e8bd5f2f3a54ff59d6.zip |
PCI: Mask writes to RO bits in the command reg of PCI config space
The Command register in the PCI config space has some read-only bits.
Any writes to those bits should be masked out.
Signed-off-by: Amit Shah <amit.shah@redhat.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6092 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'hw/pci.h')
-rw-r--r-- | hw/pci.h | 5 |
1 files changed, 5 insertions, 0 deletions
@@ -69,6 +69,11 @@ typedef struct PCIIORegion { #define PCI_STATUS_RESERVED_MASK_HI (PCI_STATUS_DEVSEL >> 8) +/* Bits in the PCI Command Register (PCI 2.3 spec) */ +#define PCI_COMMAND_RESERVED 0xf800 + +#define PCI_COMMAND_RESERVED_MASK_HI (PCI_COMMAND_RESERVED >> 8) + struct PCIDevice { /* PCI config space */ uint8_t config[256]; |