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| author | Alexander Graf <agraf@suse.de> | 2010-12-08 12:05:37 +0100 |
|---|---|---|
| committer | Blue Swirl <blauwirbel@gmail.com> | 2010-12-11 15:24:25 +0000 |
| commit | a5f59f1d30ba99ce5011b799cd5dfe2ffb3d13a0 (patch) | |
| tree | 949765d6112d70536a3806eb822798a0e04577da /hw/mcf5208.c | |
| parent | bd2320db7444ac1c67d89eed54e248d4c09e2e92 (diff) | |
| download | qemu-a5f59f1d30ba99ce5011b799cd5dfe2ffb3d13a0.tar.gz qemu-a5f59f1d30ba99ce5011b799cd5dfe2ffb3d13a0.tar.bz2 qemu-a5f59f1d30ba99ce5011b799cd5dfe2ffb3d13a0.zip | |
Add endianness as io mem parameter
As stated before, devices can be little, big or native endian. The
target endianness is not of their concern, so we need to push things
down a level.
This patch adds a parameter to cpu_register_io_memory that allows a
device to choose its endianness. For now, all devices simply choose
native endian, because that's the same behavior as before.
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'hw/mcf5208.c')
| -rw-r--r-- | hw/mcf5208.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/hw/mcf5208.c b/hw/mcf5208.c index 38645f7285..17a692d4a3 100644 --- a/hw/mcf5208.c +++ b/hw/mcf5208.c @@ -179,7 +179,8 @@ static void mcf5208_sys_init(qemu_irq *pic) int i; iomemtype = cpu_register_io_memory(m5208_sys_readfn, - m5208_sys_writefn, NULL); + m5208_sys_writefn, NULL, + DEVICE_NATIVE_ENDIAN); /* SDRAMC. */ cpu_register_physical_memory(0xfc0a8000, 0x00004000, iomemtype); /* Timers. */ @@ -188,7 +189,8 @@ static void mcf5208_sys_init(qemu_irq *pic) bh = qemu_bh_new(m5208_timer_trigger, s); s->timer = ptimer_init(bh); iomemtype = cpu_register_io_memory(m5208_timer_readfn, - m5208_timer_writefn, s); + m5208_timer_writefn, s, + DEVICE_NATIVE_ENDIAN); cpu_register_physical_memory(0xfc080000 + 0x4000 * i, 0x00004000, iomemtype); s->irq = pic[4 + i]; |