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| author | François Baldassari <francois@pebble.com> | 2015-11-19 12:09:52 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2015-11-19 12:09:52 +0000 |
| commit | a859595791e6ac5c14afe0b8a53634bf1cc21f0f (patch) | |
| tree | 30cfcf1079763b0422c399d9db0af363437d07b5 /hw/intc | |
| parent | 8f280309030331a912fd8924c129d8bd59e1bdc7 (diff) | |
| download | qemu-a859595791e6ac5c14afe0b8a53634bf1cc21f0f.tar.gz qemu-a859595791e6ac5c14afe0b8a53634bf1cc21f0f.tar.bz2 qemu-a859595791e6ac5c14afe0b8a53634bf1cc21f0f.zip | |
hw/arm_gic: Correctly restore nested irq priority
Upon activating an interrupt, set the corresponding priority bit in the
APR/NSAPR registers without touching the currently set bits. In the event
of nested interrupts, the GIC will then have the information it needs to
restore the priority of the pre-empted interrupt once the higher priority
interrupt finishes execution.
Signed-off-by: François Baldassari <francois@pebble.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/intc')
| -rw-r--r-- | hw/intc/arm_gic.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index d71aeb8a2a..13e297d52e 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -254,9 +254,9 @@ static void gic_activate_irq(GICState *s, int cpu, int irq) int bitno = preemption_level % 32; if (gic_has_groups(s) && GIC_TEST_GROUP(irq, (1 << cpu))) { - s->nsapr[regno][cpu] &= (1 << bitno); + s->nsapr[regno][cpu] |= (1 << bitno); } else { - s->apr[regno][cpu] &= (1 << bitno); + s->apr[regno][cpu] |= (1 << bitno); } s->running_priority[cpu] = prio; |