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| author | Peter Xu <peterx@redhat.com> | 2016-07-14 13:56:22 +0800 |
|---|---|---|
| committer | Michael S. Tsirkin <mst@redhat.com> | 2016-07-20 19:31:04 +0300 |
| commit | 651e4cefeee8e388919e51f4e299033ab2a8b87d (patch) | |
| tree | c9eb2dedbfb664eb17b89b2b9983febd081ee20f /hw/i386/intel_iommu_internal.h | |
| parent | a4ca297e848a3eda39acaec6941fed4eb35916df (diff) | |
| download | qemu-651e4cefeee8e388919e51f4e299033ab2a8b87d.tar.gz qemu-651e4cefeee8e388919e51f4e299033ab2a8b87d.tar.bz2 qemu-651e4cefeee8e388919e51f4e299033ab2a8b87d.zip | |
intel_iommu: Add support for PCI MSI remap
This patch enables interrupt remapping for PCI devices.
To play the trick, one memory region "iommu_ir" is added as child region
of the original iommu memory region, covering range 0xfeeXXXXX (which is
the address range for APIC). All the writes to this range will be taken
as MSI, and translation is carried out only when IR is enabled.
Idea suggested by Paolo Bonzini.
Signed-off-by: Peter Xu <peterx@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Diffstat (limited to 'hw/i386/intel_iommu_internal.h')
| -rw-r--r-- | hw/i386/intel_iommu_internal.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index 2a9987fbc4..e1a08cb496 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -110,6 +110,8 @@ /* Interrupt Address Range */ #define VTD_INTERRUPT_ADDR_FIRST 0xfee00000ULL #define VTD_INTERRUPT_ADDR_LAST 0xfeefffffULL +#define VTD_INTERRUPT_ADDR_SIZE (VTD_INTERRUPT_ADDR_LAST - \ + VTD_INTERRUPT_ADDR_FIRST + 1) /* The shift of source_id in the key of IOTLB hash table */ #define VTD_IOTLB_SID_SHIFT 36 |