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| author | Maksim Kozlov <m.kozlov@samsung.com> | 2012-02-16 09:56:05 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2012-02-17 11:13:02 +0000 |
| commit | e5a4914efc75c8880d7088dc0871766e5b73673f (patch) | |
| tree | 33afd8bb2d8c22854aef02d872802e9e89cf2f6a /hw/exynos4210.c | |
| parent | 0caa711335a676225041d014d49e65992f9f269f (diff) | |
| download | qemu-e5a4914efc75c8880d7088dc0871766e5b73673f.tar.gz qemu-e5a4914efc75c8880d7088dc0871766e5b73673f.tar.bz2 qemu-e5a4914efc75c8880d7088dc0871766e5b73673f.zip | |
ARM: exynos4210: UART support
Add basic support of exynos4210 UART
Signed-off-by: Maksim Kozlov <m.kozlov@samsung.com>
Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/exynos4210.c')
| -rw-r--r-- | hw/exynos4210.c | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/hw/exynos4210.c b/hw/exynos4210.c index 5b1e24c6c4..555adc0dda 100644 --- a/hw/exynos4210.c +++ b/hw/exynos4210.c @@ -29,6 +29,18 @@ #define EXYNOS4210_CHIPID_ADDR 0x10000000 +/* UART's definitions */ +#define EXYNOS4210_UART0_BASE_ADDR 0x13800000 +#define EXYNOS4210_UART1_BASE_ADDR 0x13810000 +#define EXYNOS4210_UART2_BASE_ADDR 0x13820000 +#define EXYNOS4210_UART3_BASE_ADDR 0x13830000 +#define EXYNOS4210_UART0_FIFO_SIZE 256 +#define EXYNOS4210_UART1_FIFO_SIZE 64 +#define EXYNOS4210_UART2_FIFO_SIZE 16 +#define EXYNOS4210_UART3_FIFO_SIZE 16 +/* Interrupt Group of External Interrupt Combiner for UART */ +#define EXYNOS4210_UART_INT_GRP 26 + /* External GIC */ #define EXYNOS4210_EXT_GIC_CPU_BASE_ADDR 0x10480000 #define EXYNOS4210_EXT_GIC_DIST_BASE_ADDR 0x10490000 @@ -187,5 +199,22 @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem, memory_region_add_subregion(system_mem, EXYNOS4210_DRAM0_BASE_ADDR, &s->dram0_mem); + /*** UARTs ***/ + exynos4210_uart_create(EXYNOS4210_UART0_BASE_ADDR, + EXYNOS4210_UART0_FIFO_SIZE, 0, NULL, + s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 0)]); + + exynos4210_uart_create(EXYNOS4210_UART1_BASE_ADDR, + EXYNOS4210_UART1_FIFO_SIZE, 1, NULL, + s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 1)]); + + exynos4210_uart_create(EXYNOS4210_UART2_BASE_ADDR, + EXYNOS4210_UART2_FIFO_SIZE, 2, NULL, + s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 2)]); + + exynos4210_uart_create(EXYNOS4210_UART3_BASE_ADDR, + EXYNOS4210_UART3_FIFO_SIZE, 3, NULL, + s->irq_table[exynos4210_get_irq(EXYNOS4210_UART_INT_GRP, 3)]); + return s; } |