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| author | aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> | 2009-03-07 21:47:53 +0000 |
|---|---|---|
| committer | aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> | 2009-03-07 21:47:53 +0000 |
| commit | a45db6c6fd587be85118038be3722c1dadeedfe4 (patch) | |
| tree | d550ab14245203613c096af889520e391b1d4ce7 /hw/arm_gic.c | |
| parent | 2701dfd2d02354fd4951a5387c9954de1201f5ad (diff) | |
| download | qemu-a45db6c6fd587be85118038be3722c1dadeedfe4.tar.gz qemu-a45db6c6fd587be85118038be3722c1dadeedfe4.tar.bz2 qemu-a45db6c6fd587be85118038be3722c1dadeedfe4.zip | |
arm: Fix gic_irq_state.level bitfield type
Found while cleaning up compiler warnings: GIC_*_LEVEL macros strongly
suggest that gic_irq_state.level is intended to be per-CPU and not just
a single, global bit. I'm unable to test the effect, but it seems to be
the most reasonable fix for the apparent brokenness.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6765 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'hw/arm_gic.c')
| -rw-r--r-- | hw/arm_gic.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/arm_gic.c b/hw/arm_gic.c index fef311334a..8e61b6e572 100644 --- a/hw/arm_gic.c +++ b/hw/arm_gic.c @@ -39,7 +39,7 @@ typedef struct gic_irq_state unsigned enabled:1; unsigned pending:NCPU; unsigned active:NCPU; - unsigned level:1; + unsigned level:NCPU; unsigned model:1; /* 0 = N:N, 1 = 1:N */ unsigned trigger:1; /* nonzero = edge triggered. */ } gic_irq_state; |