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author | Alex Bennée <alex.bennee@linaro.org> | 2014-02-20 10:35:50 +0000 |
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committer | Peter Maydell <peter.maydell@linaro.org> | 2014-02-20 10:35:50 +0000 |
commit | bc242f9bb6324a50e7572c0997904b66b630f73a (patch) | |
tree | 0916b1ccca6092ae4782443b8d90af8fa288c147 /fpu | |
parent | 8908f4d1850dbfd0de442e8deaed2f41821cdb89 (diff) | |
download | qemu-bc242f9bb6324a50e7572c0997904b66b630f73a.tar.gz qemu-bc242f9bb6324a50e7572c0997904b66b630f73a.tar.bz2 qemu-bc242f9bb6324a50e7572c0997904b66b630f73a.zip |
target-arm: A64: Implement floating point pairwise insns
Add support for the floating-point pairwise operations
FADDP, FMAXP, FMAXNMP, FMINP and FMINNMP. To do this we use the
code which was previously handling only integer pairwise operations,
and push the integer-specific decode and handling of unallocated
cases up one level in the call tree, so we can also call it from
the floating-point section of the decoder.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'fpu')
0 files changed, 0 insertions, 0 deletions