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| author | aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> | 2009-01-14 19:40:46 +0000 |
|---|---|---|
| committer | aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> | 2009-01-14 19:40:46 +0000 |
| commit | e9203484cba1f15b81e38d0b1be78806d8d66174 (patch) | |
| tree | 2b52146cf3ebfb40f5accde2b150a78478a9ce75 | |
| parent | 6958549d4f9ff6016784ff09d5898e084a15c59c (diff) | |
| download | qemu-e9203484cba1f15b81e38d0b1be78806d8d66174.tar.gz qemu-e9203484cba1f15b81e38d0b1be78806d8d66174.tar.bz2 qemu-e9203484cba1f15b81e38d0b1be78806d8d66174.zip | |
target-mips: optimize some gpr accesses
Optimize gpr accesses when it is known at translation time that gpr != 0.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6307 c046a42c-6fe2-441c-8c8c-71466251a162
| -rw-r--r-- | target-mips/translate.c | 18 |
1 files changed, 6 insertions, 12 deletions
diff --git a/target-mips/translate.c b/target-mips/translate.c index 19893a5ef4..0bfbeec6ae 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -988,9 +988,8 @@ static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt, } else if (offset == 0) { gen_load_gpr(t0, base); } else { - gen_load_gpr(t0, base); - tcg_gen_movi_tl(t1, offset); - gen_op_addr_add(ctx, t0, t1); + tcg_gen_movi_tl(t0, offset); + gen_op_addr_add(ctx, t0, cpu_gpr[base]); } /* Don't do NOP if destination is zero: we must perform the actual memory access. */ @@ -1151,12 +1150,8 @@ static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft, } else if (offset == 0) { gen_load_gpr(t0, base); } else { - TCGv t1 = tcg_temp_local_new(); - - gen_load_gpr(t0, base); - tcg_gen_movi_tl(t1, offset); - gen_op_addr_add(ctx, t0, t1); - tcg_temp_free(t1); + tcg_gen_movi_tl(t0, offset); + gen_op_addr_add(ctx, t0, cpu_gpr[base]); } /* Don't do NOP if destination is zero: we must perform the actual memory access. */ @@ -7259,9 +7254,8 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc, } else if (index == 0) { gen_load_gpr(t0, base); } else { - gen_load_gpr(t0, base); - gen_load_gpr(t1, index); - gen_op_addr_add(ctx, t0, t1); + gen_load_gpr(t0, index); + gen_op_addr_add(ctx, t0, cpu_gpr[base]); } /* Don't do NOP if destination is zero: we must perform the actual memory access. */ |