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author | David Gibson <david@gibson.dropbear.id.au> | 2011-08-03 21:02:17 +0000 |
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committer | Alexander Graf <agraf@suse.de> | 2011-10-06 09:48:02 +0200 |
commit | d5b2a441c5b584ffa89ceb41556c6ba47770071c (patch) | |
tree | 496df49a27f5e49b7de5a5f2959cbfb7000d68d2 | |
parent | dc21fbdca0658ae8899ce86449db5ad616c39935 (diff) | |
download | qemu-d5b2a441c5b584ffa89ceb41556c6ba47770071c.tar.gz qemu-d5b2a441c5b584ffa89ceb41556c6ba47770071c.tar.bz2 qemu-d5b2a441c5b584ffa89ceb41556c6ba47770071c.zip |
pseries: Add a phandle to the xicp interrupt controller device tree node
Future devices we will be adding to the pseries machine (e.g. PCI) will
need nodes in the device tree which explicitly reference the top-level
interrupt controller via interrupt-parent or interrupt-map properties.
In order to do this, the interrupt controller node needs an assigned
phandle. This patch adds the appropriate property, in preparation.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Alexander Graf <agraf@suse.de>
-rw-r--r-- | hw/spapr.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/hw/spapr.c b/hw/spapr.c index 760e3231d1..bb00ae6a6f 100644 --- a/hw/spapr.c +++ b/hw/spapr.c @@ -57,6 +57,8 @@ #define MAX_CPUS 256 #define XICS_IRQS 1024 +#define PHANDLE_XICP 0x00001111 + sPAPREnvironment *spapr; static void *spapr_create_fdt_skel(const char *cpu_model, @@ -202,6 +204,9 @@ static void *spapr_create_fdt_skel(const char *cpu_model, _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges", interrupt_server_ranges_prop, sizeof(interrupt_server_ranges_prop)))); + _FDT((fdt_property_cell(fdt, "#interrupt-cells", 2))); + _FDT((fdt_property_cell(fdt, "linux,phandle", PHANDLE_XICP))); + _FDT((fdt_property_cell(fdt, "phandle", PHANDLE_XICP))); _FDT((fdt_end_node(fdt))); |