diff options
| author | Rabin Vincent <rabinv@axis.com> | 2016-08-15 13:59:32 +0200 |
|---|---|---|
| committer | Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 2016-09-28 11:30:59 +0200 |
| commit | ceffd34e8589a9a4f18849a21ae1fecaef3af02e (patch) | |
| tree | 6c66889ab531bb93e0d73a7add944c7dac640e0c | |
| parent | 17bc37b75ea4c33a6f36f073a67df687bef840c9 (diff) | |
| download | qemu-ceffd34e8589a9a4f18849a21ae1fecaef3af02e.tar.gz qemu-ceffd34e8589a9a4f18849a21ae1fecaef3af02e.tar.bz2 qemu-ceffd34e8589a9a4f18849a21ae1fecaef3af02e.zip | |
target-cris: add v17 CPU
In the CRIS v17 CPU an ADDC (add with carry) instruction has been added
compared to the v10 instruction set.
Assembler syntax:
ADDC [Rs],Rd
ADDC [Rs+],Rd
Size: Dword
Description:
The source data is added together with the carry flag to the
destination register. The size of the operation is dword.
Operation:
Rd += s + C-flag;
Flags affected:
S R P U I X N Z V C
- - - - - 0 * * * *
Instruction format: ADDC [Rs],Rd
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
|Destination(Rd)| 1 0 0 1 1 0 1 0 | Source(Rs) |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
Instruction format: ADDC [Rs+],Rd
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
|Destination(Rd)| 1 1 0 1 1 0 1 0 | Source(Rs) |
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
[EI: Shorten 80+ lines]
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Rabin Vincent <rabinv@axis.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
| -rw-r--r-- | target-cris/cpu.c | 14 | ||||
| -rw-r--r-- | target-cris/crisv10-decode.h | 1 | ||||
| -rw-r--r-- | target-cris/translate_v10.c | 23 |
3 files changed, 38 insertions, 0 deletions
diff --git a/target-cris/cpu.c b/target-cris/cpu.c index c5a656bb62..d680cfb52b 100644 --- a/target-cris/cpu.c +++ b/target-cris/cpu.c @@ -246,6 +246,16 @@ static void crisv11_cpu_class_init(ObjectClass *oc, void *data) cc->gdb_read_register = crisv10_cpu_gdb_read_register; } +static void crisv17_cpu_class_init(ObjectClass *oc, void *data) +{ + CPUClass *cc = CPU_CLASS(oc); + CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); + + ccc->vr = 17; + cc->do_interrupt = crisv10_cpu_do_interrupt; + cc->gdb_read_register = crisv10_cpu_gdb_read_register; +} + static void crisv32_cpu_class_init(ObjectClass *oc, void *data) { CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); @@ -273,6 +283,10 @@ static const TypeInfo cris_cpu_model_type_infos[] = { .parent = TYPE_CRIS_CPU, .class_init = crisv11_cpu_class_init, }, { + .name = TYPE("crisv17"), + .parent = TYPE_CRIS_CPU, + .class_init = crisv17_cpu_class_init, + }, { .name = TYPE("crisv32"), .parent = TYPE_CRIS_CPU, .class_init = crisv32_cpu_class_init, diff --git a/target-cris/crisv10-decode.h b/target-cris/crisv10-decode.h index 587fbdd278..bdb4b6d318 100644 --- a/target-cris/crisv10-decode.h +++ b/target-cris/crisv10-decode.h @@ -92,6 +92,7 @@ #define CRISV10_IND_JUMP_M 4 #define CRISV10_IND_DIP 5 #define CRISV10_IND_JUMP_R 6 +#define CRISV17_IND_ADDC 6 #define CRISV10_IND_BOUND 7 #define CRISV10_IND_BCC_M 7 #define CRISV10_IND_MOVE_M_SPR 8 diff --git a/target-cris/translate_v10.c b/target-cris/translate_v10.c index 4707a18e77..4a0b485d8e 100644 --- a/target-cris/translate_v10.c +++ b/target-cris/translate_v10.c @@ -1094,6 +1094,29 @@ static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc) insn_len = dec10_bdap_m(env, dc, size); break; default: + /* + * ADDC for v17: + * + * Instruction format: ADDC [Rs],Rd + * + * +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+-+ + * |Destination(Rd)| 1 0 0 1 1 0 1 0 | Source(Rs)| + * +---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+ + * + * Instruction format: ADDC [Rs+],Rd + * + * +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+-+ + * |Destination(Rd)| 1 1 0 1 1 0 1 0 | Source(Rs)| + * +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+-+ + */ + if (dc->opcode == CRISV17_IND_ADDC && dc->size == 2 && + env->pregs[PR_VR] == 17) { + LOG_DIS("addc op=%d %d\n", dc->src, dc->dst); + cris_cc_mask(dc, CC_MASK_NZVC); + insn_len += dec10_ind_alu(env, dc, CC_OP_ADDC, size); + break; + } + LOG_DIS("pc=%x var-ind.%d %d r%d r%d\n", dc->pc, size, dc->opcode, dc->src, dc->dst); cpu_abort(CPU(dc->cpu), "Unhandled opcode"); |