Push common interrupt variables to cpu-defs.h (Glauber Costa)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4612 c046a42c-6fe2-441c-8c8c-71466251a162

10 files changed, 4 insertions, 18 deletions

diff --git a/cpu-defs.h b/cpu-defs.h
index 7001ca4b25..f7f5f1730d 100644
--- a/cpu-defs.h
+++ b/cpu-defs.h
@@ -160,6 +160,10 @@ typedef struct CPUTLBEntry {
     int nb_watchpoints;                                                 \
     int watchpoint_hit;                                                 \
                                                                         \
+    /* Core interrupt code */                                           \
+    jmp_buf jmp_env;                                                    \
+    int exception_index;                                                \
+                                                                        \
     void *next_cpu; /* next CPU sharing TB cache */                     \
     int cpu_index; /* CPU index (informative) */                        \
     /* user data */                                                     \
diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h
index 0331e50a7f..c955997fce 100644
--- a/target-alpha/cpu.h
+++ b/target-alpha/cpu.h
@@ -282,11 +282,9 @@ struct CPUAlphaState {
     /* Those resources are used only in Qemu core */
     CPU_COMMON
 
-    jmp_buf jmp_env;
     int user_mode_only; /* user mode only simulation */
     uint32_t hflags;
 
-    int exception_index;
     int error_code;
     int interrupt_request;
 
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index f7252f5c21..1042808665 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -157,8 +157,6 @@ typedef struct CPUARMState {
     void *irq_opaque;
 
     /* exception/interrupt handling */
-    jmp_buf jmp_env;
-    int exception_index;
     int interrupt_request;
     int user_mode_only;
 
diff --git a/target-cris/cpu.h b/target-cris/cpu.h
index 035b04fce9..14b09d8cb6 100644
--- a/target-cris/cpu.h
+++ b/target-cris/cpu.h
@@ -123,7 +123,6 @@ typedef struct CPUCRISState {
 	/* X flag at the time of cc snapshot.  */
 	int cc_x;
 
-	int exception_index;
 	int interrupt_request;
 	int interrupt_vector;
 	int fault_vector;
@@ -158,7 +157,6 @@ typedef struct CPUCRISState {
 	int features;
 	int user_mode_only;
 
-	jmp_buf jmp_env;
 	CPU_COMMON
 } CPUCRISState;
 
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index 2012debef7..eb0052786c 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -552,8 +552,6 @@ typedef struct CPUX86State {
     uint64_t pat;
 
     /* exception/interrupt handling */
-    jmp_buf jmp_env;
-    int exception_index;
     int error_code;
     int exception_is_int;
     target_ulong exception_next_eip;
diff --git a/target-m68k/cpu.h b/target-m68k/cpu.h
index 34651e3e89..d5c5a10556 100644
--- a/target-m68k/cpu.h
+++ b/target-m68k/cpu.h
@@ -104,8 +104,6 @@ typedef struct CPUM68KState {
     uint32_t t1;
 
     /* exception/interrupt handling */
-    jmp_buf jmp_env;
-    int exception_index;
     int interrupt_request;
     int user_mode_only;
 
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index cb12b3c28b..9295b531d6 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -412,8 +412,6 @@ struct CPUMIPSState {
     int32_t CP0_DESAVE;
     /* Qemu */
     int interrupt_request;
-    jmp_buf jmp_env;
-    int exception_index;
     int error_code;
     int user_mode_only; /* user mode only simulation */
     uint32_t hflags;    /* CPU State */
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 3eea695292..a884fd6333 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -646,7 +646,6 @@ struct CPUPPCState {
     int bfd_mach;
     uint32_t flags;
 
-    int exception_index;
     int error_code;
     int interrupt_request;
     uint32_t pending_interrupts;
@@ -672,7 +671,6 @@ struct CPUPPCState {
     opc_handler_t *opcodes[0x40];
 
     /* Those resources are used only in Qemu core */
-    jmp_buf jmp_env;
     int user_mode_only; /* user mode only simulation */
     target_ulong hflags;      /* hflags is a MSR & HFLAGS_MASK         */
     target_ulong hflags_nmsr; /* specific hflags, not comming from MSR */
diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h
index 812db938cd..c03cdb188c 100644
--- a/target-sh4/cpu.h
+++ b/target-sh4/cpu.h
@@ -114,10 +114,8 @@ typedef struct CPUSH4State {
     uint32_t expevt;		/* exception event register */
     uint32_t intevt;		/* interrupt event register */
 
-    jmp_buf jmp_env;
     int user_mode_only;
     int interrupt_request;
-    int exception_index;
      CPU_COMMON tlb_t utlb[UTLB_SIZE];	/* unified translation table */
     tlb_t itlb[ITLB_SIZE];	/* instruction translation table */
     void *intc_handle;
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index f00192e8c3..ba3ee01b08 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -214,9 +214,7 @@ typedef struct CPUSPARCState {
     uint32_t pil_in;   /* incoming interrupt level bitmap */
     int      psref;    /* enable fpu */
     target_ulong version;
-    jmp_buf  jmp_env;
     int user_mode_only;
-    int exception_index;
     int interrupt_index;
     int interrupt_request;
     uint32_t mmu_bm;