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| author | Peter Maydell <peter.maydell@linaro.org> | 2011-11-09 17:42:23 +0000 |
|---|---|---|
| committer | Anthony Liguori <aliguori@us.ibm.com> | 2011-11-09 12:06:20 -0600 |
| commit | c0465d1a1d4c9562cfa7e91f6c31ea1bce22052c (patch) | |
| tree | 4a6a4c4d3dc17c9ad1929b38809c0331ae7e6a19 | |
| parent | 95117be5a337d15555b69b7059d4e0791ce8063d (diff) | |
| download | qemu-c0465d1a1d4c9562cfa7e91f6c31ea1bce22052c.tar.gz qemu-c0465d1a1d4c9562cfa7e91f6c31ea1bce22052c.tar.bz2 qemu-c0465d1a1d4c9562cfa7e91f6c31ea1bce22052c.zip | |
hw/omap_gpmc.c: Add missing 'break's to fix 8 bit NAND writes
Add missing 'break' statements which would have meant that writing
to an 8 bit NAND device was broken. Spotted by Coverity (see bug
887883).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
| -rw-r--r-- | hw/omap_gpmc.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/hw/omap_gpmc.c b/hw/omap_gpmc.c index 7fc82a2526..414f9f5c37 100644 --- a/hw/omap_gpmc.c +++ b/hw/omap_gpmc.c @@ -180,6 +180,7 @@ static void omap_nand_setio(DeviceState *dev, uint64_t value, nand_setio(dev, (value >> 24) & 0xff); break; } + break; case OMAP_GPMC_16BIT: switch (size) { case 1: @@ -195,6 +196,7 @@ static void omap_nand_setio(DeviceState *dev, uint64_t value, nand_setio(dev, (value >> 16) & 0xffff); break; } + break; } } |