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| author | Tom Musta <tommusta@gmail.com> | 2014-02-12 15:23:19 -0600 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2014-03-05 03:07:00 +0100 |
| commit | ac174549b730531a4d13c8281e2247e66ba0f46d (patch) | |
| tree | 5d14392025a52e6525c84ae8c9fb562693f992ab | |
| parent | 57354f8f12d04efc3c38126b967fc178b56885f5 (diff) | |
| download | qemu-ac174549b730531a4d13c8281e2247e66ba0f46d.tar.gz qemu-ac174549b730531a4d13c8281e2247e66ba0f46d.tar.bz2 qemu-ac174549b730531a4d13c8281e2247e66ba0f46d.zip | |
target-ppc: Altivec 2.07: Vector Permute and Exclusive OR
This patch adds the Vector Permuate and Exclusive OR (vpermxor)
instruction introduced in Power ISA Version 2.07.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
| -rw-r--r-- | target-ppc/helper.h | 1 | ||||
| -rw-r--r-- | target-ppc/int_helper.c | 14 | ||||
| -rw-r--r-- | target-ppc/translate.c | 7 |
3 files changed, 21 insertions, 1 deletions
diff --git a/target-ppc/helper.h b/target-ppc/helper.h index dc0527bca2..99f10deee1 100644 --- a/target-ppc/helper.h +++ b/target-ppc/helper.h @@ -323,6 +323,7 @@ DEF_HELPER_3(vncipher, void, avr, avr, avr) DEF_HELPER_3(vncipherlast, void, avr, avr, avr) DEF_HELPER_3(vshasigmaw, void, avr, avr, i32) DEF_HELPER_3(vshasigmad, void, avr, avr, i32) +DEF_HELPER_4(vpermxor, void, avr, avr, avr, avr) DEF_HELPER_4(bcdadd, i32, avr, avr, avr, i32) DEF_HELPER_4(bcdsub, i32, avr, avr, avr, i32) diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c index e6a7ad025c..63dde94b04 100644 --- a/target-ppc/int_helper.c +++ b/target-ppc/int_helper.c @@ -2700,6 +2700,20 @@ void helper_vshasigmad(ppc_avr_t *r, ppc_avr_t *a, uint32_t st_six) #undef ROTRu64 #undef EL_IDX +void helper_vpermxor(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c) +{ + int i; + VECTOR_FOR_INORDER_I(i, u8) { + int indexA = c->u8[i] >> 4; + int indexB = c->u8[i] & 0xF; +#if defined(HOST_WORDS_BIGENDIAN) + r->u8[i] = a->u8[indexA] ^ b->u8[indexB]; +#else + r->u8[i] = a->u8[15-indexA] ^ b->u8[15-indexB]; +#endif + } +} + #undef VECTOR_FOR_INORDER_I #undef HI_IDX #undef LO_IDX diff --git a/target-ppc/translate.c b/target-ppc/translate.c index e1dffdf678..cf8f98ad1d 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -7459,6 +7459,10 @@ static void gen_##op(DisasContext *ctx) \ VSHASIGMA(vshasigmaw) VSHASIGMA(vshasigmad) +GEN_VXFORM3(vpermxor, 22, 0xFF) +GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE, + vpermxor, PPC_NONE, PPC2_ALTIVEC_207) + /*** VSX extension ***/ static inline TCGv_i64 cpu_vsrh(int n) @@ -10111,7 +10115,6 @@ GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), -GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC), GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC), GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE), GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE), @@ -10722,6 +10725,8 @@ GEN_VXFORM_DUAL(vncipher, vncipherlast, 4, 21, PPC_NONE, PPC2_ALTIVEC_207), GEN_VXFORM_207(vshasigmaw, 1, 26), GEN_VXFORM_207(vshasigmad, 1, 27), +GEN_VXFORM_DUAL(vsldoi, vpermxor, 22, 0xFF, PPC_ALTIVEC, PPC_NONE), + GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX), GEN_HANDLER_E(lxsiwax, 0x1F, 0x0C, 0x02, 0, PPC_NONE, PPC2_VSX207), GEN_HANDLER_E(lxsiwzx, 0x1F, 0x0C, 0x00, 0, PPC_NONE, PPC2_VSX207), |