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| author | Peter Maydell <peter.maydell@linaro.org> | 2014-03-17 16:31:50 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-03-17 16:31:50 +0000 |
| commit | a566da1b02704a79038043ddbe850f40b033cd63 (patch) | |
| tree | 2c5aba4590693ddf9ea0e447b30d2d832305a942 | |
| parent | 931c8cc270793877f8d7bf9934ac9fa3fb7800be (diff) | |
| download | qemu-a566da1b02704a79038043ddbe850f40b033cd63.tar.gz qemu-a566da1b02704a79038043ddbe850f40b033cd63.tar.bz2 qemu-a566da1b02704a79038043ddbe850f40b033cd63.zip | |
target-arm: A64: List unsupported shift-imm opcodes
Add the remaining unsupported opcodes to the decode switches
for the shift-imm and scalar shift-imm categories so we can
see what is still to be implemented.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-id: 1394822294-14837-13-git-send-email-peter.maydell@linaro.org
| -rw-r--r-- | target-arm/translate-a64.c | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index e6addf45f1..2b1ca64b19 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -6135,9 +6135,15 @@ static void disas_simd_scalar_shift_imm(DisasContext *s, uint32_t insn) handle_vec_simd_sqshrn(s, true, false, is_u, is_u, immh, immb, opcode, rn, rd); break; - default: + case 0x8: /* SRI */ + case 0xc: /* SQSHLU */ + case 0xe: /* SQSHL, UQSHL */ + case 0x1f: /* FCVTZS, FCVTZU */ unsupported_encoding(s, insn); break; + default: + unallocated_encoding(s); + break; } } @@ -7281,11 +7287,14 @@ static void disas_simd_shift_imm(DisasContext *s, uint32_t insn) handle_simd_shift_intfp_conv(s, false, is_q, is_u, immh, immb, opcode, rn, rd); break; + case 0x8: /* SRI */ + case 0xc: /* SQSHLU */ + case 0xe: /* SQSHL, UQSHL */ case 0x1f: /* FCVTZS/ FCVTZU */ unsupported_encoding(s, insn); return; default: - unsupported_encoding(s, insn); + unallocated_encoding(s); return; } } |