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authorAndrew Jeffery <andrew@aj.id.au>2016-06-27 15:37:33 +0100
committerPeter Maydell <peter.maydell@linaro.org>2016-06-27 15:37:33 +0100
commit87e79af074ba96a3307447939ae196324b34eb3d (patch)
tree0dc5bb64b765f841b54a6d770d93409ce44c93e7
parent334973bbae19788559f940966c8e3a208edbb1ee (diff)
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palmetto-bmc: Configure the SCU's hardware strapping register
The magic constant configures the following options: * 28:27: Configure DRAM size as 256MB * 26:24: DDR3 SDRAM with CL = 6, CWL = 5 * 23: Configure 24/48MHz CLKIN * 22: Disable GPIOE pass-through mode * 21: Disable GPIOD pass-through mode * 20: Enable LPC decode of SuperIO 0x2E/0x4E addresses * 19: Disable ACPI * 18: Configure 48MHz CLKIN * 17: Disable BMC 2nd boot watchdog timer * 16: Decode SuperIO address 0x2E * 15: VGA Class Code * 14: Enable LPC dedicated reset pin * 13:12: Enable SPI Master and SPI Slave to AHB Bridge * 11:10: Select CPU:AHB ratio = 2:1 * 9:8: Select 384MHz H-PLL * 7: Configure MAC#2 for RMII/NCSI * 6: Configure MAC#1 for RMII/NCSI * 5: No VGA BIOS ROM * 4: Boot using 32bit SPI address mode * 3:2: Select 16MB VGA memory * 1:0: Boot from SPI flash memory Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Cédric Le Goater <clg@kaod.org> Message-id: 1466744305-23163-4-git-send-email-andrew@aj.id.au Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r--hw/arm/palmetto-bmc.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/hw/arm/palmetto-bmc.c b/hw/arm/palmetto-bmc.c
index a51d960510..b8eed21348 100644
--- a/hw/arm/palmetto-bmc.c
+++ b/hw/arm/palmetto-bmc.c
@@ -44,6 +44,8 @@ static void palmetto_bmc_init(MachineState *machine)
&bmc->ram);
object_property_add_const_link(OBJECT(&bmc->soc), "ram", OBJECT(&bmc->ram),
&error_abort);
+ object_property_set_int(OBJECT(&bmc->soc), 0x120CE416, "hw-strap1",
+ &error_abort);
object_property_set_bool(OBJECT(&bmc->soc), true, "realized",
&error_abort);