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| author | aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> | 2009-04-05 20:08:50 +0000 |
|---|---|---|
| committer | aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> | 2009-04-05 20:08:50 +0000 |
| commit | 4eb5f7b6cf7e62db40780d3ada330204ed5a23d3 (patch) | |
| tree | 1b3f0b34a8d1632d6104c8d9eee1142c41fc2d38 | |
| parent | cf6f1e7efbe07c064e418564f704ed5e6ee8bbe0 (diff) | |
| download | qemu-4eb5f7b6cf7e62db40780d3ada330204ed5a23d3.tar.gz qemu-4eb5f7b6cf7e62db40780d3ada330204ed5a23d3.tar.bz2 qemu-4eb5f7b6cf7e62db40780d3ada330204ed5a23d3.zip | |
tcg/x86_64: optimize register allocation order
The beginning of the register allocation order list on the TCG x86_64
target matches the list of clobbered registers. This means that when an
helper is called, there is almost always clobbered registers that have
to be spilled.
The same way register %rsi and %rdi are at the top of the register
allocation order list, while they can't be used for load/store
operations. This means the data and/or address registers are very often
%rsi and %rdi, and their values have to be spilled, and then moved back
to another register.
This patches changes to the allocation order to avoid those effects.
It results in a 8% gain speed in qemu-x86_64 to compress a bzip2 file,
and a 6% gain in qemu-system-mips64 to compile a small application.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7003 c046a42c-6fe2-441c-8c8c-71466251a162
| -rw-r--r-- | tcg/x86_64/tcg-target.c | 19 |
1 files changed, 9 insertions, 10 deletions
diff --git a/tcg/x86_64/tcg-target.c b/tcg/x86_64/tcg-target.c index 92f0733efe..5378e8510b 100644 --- a/tcg/x86_64/tcg-target.c +++ b/tcg/x86_64/tcg-target.c @@ -44,22 +44,21 @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { #endif static const int tcg_target_reg_alloc_order[] = { - TCG_REG_RDI, - TCG_REG_RSI, - TCG_REG_RDX, - TCG_REG_RCX, - TCG_REG_R8, - TCG_REG_R9, - TCG_REG_RAX, - TCG_REG_R10, - TCG_REG_R11, - TCG_REG_RBP, TCG_REG_RBX, TCG_REG_R12, TCG_REG_R13, TCG_REG_R14, TCG_REG_R15, + TCG_REG_R10, + TCG_REG_R11, + TCG_REG_R9, + TCG_REG_R8, + TCG_REG_RCX, + TCG_REG_RDX, + TCG_REG_RSI, + TCG_REG_RDI, + TCG_REG_RAX, }; static const int tcg_target_call_iarg_regs[6] = { |