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author | Blue Swirl <blauwirbel@gmail.com> | 2009-05-10 10:38:34 +0300 |
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committer | Blue Swirl <blauwirbel@gmail.com> | 2009-05-10 10:38:34 +0300 |
commit | 2ca1d92b0785b65c48b415ee9074f3674432edde (patch) | |
tree | 784864e9b4201f412b7c28fb2a66005a028858b3 | |
parent | d4b0d46898ec67e733b64b14d623550d1e7f6b9d (diff) | |
download | qemu-2ca1d92b0785b65c48b415ee9074f3674432edde.tar.gz qemu-2ca1d92b0785b65c48b415ee9074f3674432edde.tar.bz2 qemu-2ca1d92b0785b65c48b415ee9074f3674432edde.zip |
Convert subx
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
-rw-r--r-- | target-sparc/op_helper.c | 44 | ||||
-rw-r--r-- | target-sparc/translate.c | 37 |
2 files changed, 50 insertions, 31 deletions
diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c index 5890f2902d..0df6bb045a 100644 --- a/target-sparc/op_helper.c +++ b/target-sparc/op_helper.c @@ -972,6 +972,48 @@ static uint32_t compute_C_sub_xcc(void) } #endif +static uint32_t compute_all_subx(void) +{ + uint32_t ret; + + ret = get_NZ_icc(CC_DST); + ret |= get_C_sub_icc(CC_DST - CC_SRC2, CC_SRC); + ret |= get_C_sub_icc(CC_DST, CC_SRC2); + ret |= get_V_sub_icc(CC_DST, CC_SRC, CC_SRC2); + return ret; +} + +static uint32_t compute_C_subx(void) +{ + uint32_t ret; + + ret = get_C_sub_icc(CC_DST - CC_SRC2, CC_SRC); + ret |= get_C_sub_icc(CC_DST, CC_SRC2); + return ret; +} + +#ifdef TARGET_SPARC64 +static uint32_t compute_all_subx_xcc(void) +{ + uint32_t ret; + + ret = get_NZ_xcc(CC_DST); + ret |= get_C_sub_xcc(CC_DST - CC_SRC2, CC_SRC); + ret |= get_C_sub_xcc(CC_DST, CC_SRC2); + ret |= get_V_sub_xcc(CC_DST, CC_SRC, CC_SRC2); + return ret; +} + +static uint32_t compute_C_subx_xcc(void) +{ + uint32_t ret; + + ret = get_C_sub_xcc(CC_DST - CC_SRC2, CC_SRC); + ret |= get_C_sub_xcc(CC_DST, CC_SRC2); + return ret; +} +#endif + static uint32_t compute_all_logic(void) { return get_NZ_icc(CC_DST); @@ -1000,6 +1042,7 @@ static const CCTable icc_table[CC_OP_NB] = { [CC_OP_ADD] = { compute_all_add, compute_C_add }, [CC_OP_ADDX] = { compute_all_addx, compute_C_addx }, [CC_OP_SUB] = { compute_all_sub, compute_C_sub }, + [CC_OP_SUBX] = { compute_all_subx, compute_C_subx }, [CC_OP_LOGIC] = { compute_all_logic, compute_C_logic }, }; @@ -1010,6 +1053,7 @@ static const CCTable xcc_table[CC_OP_NB] = { [CC_OP_ADD] = { compute_all_add_xcc, compute_C_add_xcc }, [CC_OP_ADDX] = { compute_all_addx_xcc, compute_C_addx_xcc }, [CC_OP_SUB] = { compute_all_sub_xcc, compute_C_sub_xcc }, + [CC_OP_SUBX] = { compute_all_subx_xcc, compute_C_subx_xcc }, [CC_OP_LOGIC] = { compute_all_logic_xcc, compute_C_logic }, }; #endif diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 040e0f0794..f4d3fbed57 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -635,33 +635,14 @@ static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2) tcg_gen_mov_tl(dst, cpu_cc_dst); } -static inline void gen_op_subx_cc2(TCGv dst) -{ - gen_cc_NZ_icc(cpu_cc_dst); - gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src); - gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); -#ifdef TARGET_SPARC64 - gen_cc_NZ_xcc(cpu_cc_dst); - gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src); - gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2); -#endif - tcg_gen_mov_tl(dst, cpu_cc_dst); -} - static inline void gen_op_subxi_cc(TCGv dst, TCGv src1, target_long src2) { tcg_gen_mov_tl(cpu_cc_src, src1); tcg_gen_movi_tl(cpu_cc_src2, src2); gen_mov_reg_C(cpu_tmp0, cpu_psr); tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0); - gen_cc_clear_icc(); - gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src); -#ifdef TARGET_SPARC64 - gen_cc_clear_xcc(); - gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src); -#endif tcg_gen_subi_tl(cpu_cc_dst, cpu_cc_dst, src2); - gen_op_subx_cc2(dst); + tcg_gen_mov_tl(dst, cpu_cc_dst); } static inline void gen_op_subx_cc(TCGv dst, TCGv src1, TCGv src2) @@ -670,14 +651,8 @@ static inline void gen_op_subx_cc(TCGv dst, TCGv src1, TCGv src2) tcg_gen_mov_tl(cpu_cc_src2, src2); gen_mov_reg_C(cpu_tmp0, cpu_psr); tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0); - gen_cc_clear_icc(); - gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src); -#ifdef TARGET_SPARC64 - gen_cc_clear_xcc(); - gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src); -#endif tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_dst, cpu_cc_src2); - gen_op_subx_cc2(dst); + tcg_gen_mov_tl(dst, cpu_cc_dst); } static inline void gen_op_tsub_cc(TCGv dst, TCGv src1, TCGv src2) @@ -3263,8 +3238,8 @@ static void disas_sparc_insn(DisasContext * dc) if (xop & 0x10) { gen_helper_compute_psr(); gen_op_subxi_cc(cpu_dst, cpu_src1, simm); - tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS); - dc->cc_op = CC_OP_FLAGS; + tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUBX); + dc->cc_op = CC_OP_SUBX; } else { gen_helper_compute_psr(); gen_mov_reg_C(cpu_tmp0, cpu_psr); @@ -3275,8 +3250,8 @@ static void disas_sparc_insn(DisasContext * dc) if (xop & 0x10) { gen_helper_compute_psr(); gen_op_subx_cc(cpu_dst, cpu_src1, cpu_src2); - tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS); - dc->cc_op = CC_OP_FLAGS; + tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUBX); + dc->cc_op = CC_OP_SUBX; } else { gen_helper_compute_psr(); gen_mov_reg_C(cpu_tmp0, cpu_psr); |