diff options
Diffstat (limited to 'tests/gem_pipe_control_store_loop.c')
| -rw-r--r-- | tests/gem_pipe_control_store_loop.c | 121 |
1 files changed, 67 insertions, 54 deletions
diff --git a/tests/gem_pipe_control_store_loop.c b/tests/gem_pipe_control_store_loop.c index e03cddd7..c95c2bdf 100644 --- a/tests/gem_pipe_control_store_loop.c +++ b/tests/gem_pipe_control_store_loop.c @@ -34,18 +34,18 @@ #include <stdlib.h> #include <stdio.h> #include <string.h> -#include <assert.h> #include <fcntl.h> #include <inttypes.h> #include <errno.h> #include <sys/stat.h> #include <sys/time.h> #include "drm.h" -#include "i915_drm.h" +#include "ioctl_wrappers.h" #include "drmtest.h" #include "intel_bufmgr.h" #include "intel_batchbuffer.h" -#include "intel_gpu_tools.h" +#include "intel_chipset.h" +#include "intel_io.h" static drm_intel_bufmgr *bufmgr; struct intel_batchbuffer *batch; @@ -64,25 +64,54 @@ uint32_t devid; /* Like the store dword test, but we create new command buffers each time */ static void -store_pipe_control_loop(void) +store_pipe_control_loop(bool preuse_buffer) { int i, val = 0; uint32_t *buf; drm_intel_bo *target_bo; - for (i = 0; i < 0x10000; i++) { + for (i = 0; i < SLOW_QUICK(0x10000, 4); i++) { /* we want to check tlb consistency of the pipe_control target, * so get a new buffer every time around */ target_bo = drm_intel_bo_alloc(bufmgr, "target bo", 4096, 4096); - if (!target_bo) { - fprintf(stderr, "failed to alloc target buffer\n"); - exit(-1); + igt_assert(target_bo); + + if (preuse_buffer) { + COLOR_BLIT_COPY_BATCH_START(devid, 0); + OUT_BATCH((3 << 24) | (0xf0 << 16) | 64); + OUT_BATCH(0); + OUT_BATCH(1 << 16 | 1); + + /* + * IMPORTANT: We need to preuse the buffer in a + * different domain than what the pipe control write + * (and kernel wa) uses! + */ + OUT_RELOC(target_bo, + I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, + 0); + BLIT_RELOC_UDW(devid); + OUT_BATCH(0xdeadbeef); + ADVANCE_BATCH(); + + intel_batchbuffer_flush(batch); } /* gem_storedw_batches_loop.c is a bit overenthusiastic with * creating new batchbuffers - with buffer reuse disabled, the * support code will do that for us. */ - if (intel_gen(devid) >= 6) { + if (intel_gen(devid) >= 8) { + BEGIN_BATCH(5); + OUT_BATCH(GFX_OP_PIPE_CONTROL + 1); + OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE); + OUT_RELOC(target_bo, + I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, + PIPE_CONTROL_GLOBAL_GTT); + BLIT_RELOC_UDW(devid); + OUT_BATCH(val); /* write data */ + ADVANCE_BATCH(); + + } else if (intel_gen(devid) >= 6) { /* work-around hw issue, see intel_emit_post_sync_nonzero_flush * in mesa sources. */ BEGIN_BATCH(4); @@ -119,66 +148,50 @@ store_pipe_control_loop(void) drm_intel_bo_map(target_bo, 1); buf = target_bo->virtual; - if (buf[0] != val) { - fprintf(stderr, - "value mismatch: cur 0x%08x, stored 0x%08x\n", - buf[0], val); - exit(-1); - } - buf[0] = 0; /* let batch write it again */ - drm_intel_bo_unmap(target_bo); + igt_assert(buf[0] == val); + drm_intel_bo_unmap(target_bo); + /* Make doublesure that this buffer won't get reused. */ + drm_intel_bo_disable_reuse(target_bo); drm_intel_bo_unreference(target_bo); val++; } - - printf("completed %d writes successfully\n", i); } -int main(int argc, char **argv) +int fd; + +igt_main { - int fd; + igt_fixture { + fd = drm_open_any(); + devid = intel_get_drm_devid(fd); - if (argc != 1) { - fprintf(stderr, "usage: %s\n", argv[0]); - exit(-1); - } + bufmgr = drm_intel_bufmgr_gem_init(fd, 4096); + igt_assert(bufmgr); - fd = drm_open_any(); - devid = intel_get_drm_devid(fd); + igt_skip_on(IS_GEN2(devid) || IS_GEN3(devid)); + igt_skip_on(devid == PCI_CHIP_I965_G); /* has totally broken pipe control */ - bufmgr = drm_intel_bufmgr_gem_init(fd, 4096); - if (!bufmgr) { - fprintf(stderr, "failed to init libdrm\n"); - exit(-1); - } + /* IMPORTANT: No call to + * drm_intel_bufmgr_gem_enable_reuse(bufmgr); + * here because we wan't to have fresh buffers (to trash the tlb) + * every time! */ - if (IS_GEN2(devid) || IS_GEN3(devid)) { - fprintf(stderr, "no pipe_control on gen2/3\n"); - return 77; - } - if (devid == PCI_CHIP_I965_G) { - fprintf(stderr, "pipe_control totally broken on i965\n"); - return 77; - } - /* IMPORTANT: No call to - * drm_intel_bufmgr_gem_enable_reuse(bufmgr); - * here because we wan't to have fresh buffers (to trash the tlb) - * every time! */ - - batch = intel_batchbuffer_alloc(bufmgr, devid); - if (!batch) { - fprintf(stderr, "failed to create batch buffer\n"); - exit(-1); + batch = intel_batchbuffer_alloc(bufmgr, devid); + igt_assert(batch); } - store_pipe_control_loop(); + igt_subtest("fresh-buffer") + store_pipe_control_loop(false); - intel_batchbuffer_free(batch); - drm_intel_bufmgr_destroy(bufmgr); + igt_subtest("reused-buffer") + store_pipe_control_loop(true); - close(fd); + igt_fixture { + intel_batchbuffer_free(batch); + drm_intel_bufmgr_destroy(bufmgr); - return 0; + close(fd); + } } |