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| author | Ed Lin <ed.lin@promise.com> | 2007-05-09 20:50:37 -0800 |
|---|---|---|
| committer | James Bottomley <jejb@mulgrave.il.steeleye.com> | 2007-05-16 12:40:51 -0400 |
| commit | 69f4a513911455670d3322fb5252b437c0485707 (patch) | |
| tree | 15343daad98d417ed1e498a7792e6d08200a614d /drivers | |
| parent | e0b2e597d5dd8c4f3778545f65c29a9c6aba0e3a (diff) | |
| download | kernel-common-69f4a513911455670d3322fb5252b437c0485707.tar.gz kernel-common-69f4a513911455670d3322fb5252b437c0485707.tar.bz2 kernel-common-69f4a513911455670d3322fb5252b437c0485707.zip | |
[SCSI] stex: extend hard reset wait time
During hard bus reset of st_shasta controllers, 1 ms is not enough for
16-port controllers, although it's good for 8-port controllers. Extend the
wait time to 100 ms to allow bus resets finish successfully.
Signed-off-by: Ed Lin <ed.lin@promise.com>
Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/scsi/stex.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/drivers/scsi/stex.c b/drivers/scsi/stex.c index 96dcbac9545e..81dd3b740daf 100644 --- a/drivers/scsi/stex.c +++ b/drivers/scsi/stex.c @@ -1041,7 +1041,12 @@ static void stex_hard_reset(struct st_hba *hba) pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &pci_bctl); pci_bctl |= PCI_BRIDGE_CTL_BUS_RESET; pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl); - msleep(1); + + /* + * 1 ms may be enough for 8-port controllers. But 16-port controllers + * require more time to finish bus reset. Use 100 ms here for safety + */ + msleep(100); pci_bctl &= ~PCI_BRIDGE_CTL_BUS_RESET; pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl); |