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author | Guennadi Liakhovetski <g.liakhovetski@gmx.de> | 2013-12-14 16:23:51 +0100 |
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committer | Stephane Desneux <stephane.desneux@open.eurogiciel.org> | 2015-02-04 11:12:55 +0100 |
commit | 7a84a6374a6097f1f73a7d10c8f5e86d96a7a08d (patch) | |
tree | 52d633454dedc794e9500fa871ac485b51bc4ed1 /drivers/sh | |
parent | 4b0649c3d73acc4f40dcd9a6dd503f041672f385 (diff) | |
download | kernel-common-7a84a6374a6097f1f73a7d10c8f5e86d96a7a08d.tar.gz kernel-common-7a84a6374a6097f1f73a7d10c8f5e86d96a7a08d.tar.bz2 kernel-common-7a84a6374a6097f1f73a7d10c8f5e86d96a7a08d.zip |
ARM: shmobile: wait for MSTP clock status to toggle, when enabling it
On r-/sh-mobile SoCs MSTP clocks are used by the runtime PM to dynamically
enable and disable peripheral clocks. To make sure the clock has really
started we have to read back its status register until it confirms success.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
(cherry picked from commit a028c6da34d434e35ba8322568c756ea97ff3c18)
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'drivers/sh')
-rw-r--r-- | drivers/sh/clk/cpg.c | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/drivers/sh/clk/cpg.c b/drivers/sh/clk/cpg.c index 1ebe67cd1833..7442bc130055 100644 --- a/drivers/sh/clk/cpg.c +++ b/drivers/sh/clk/cpg.c @@ -36,9 +36,47 @@ static void sh_clk_write(int value, struct clk *clk) iowrite32(value, clk->mapped_reg); } +static unsigned int r8(const void __iomem *addr) +{ + return ioread8(addr); +} + +static unsigned int r16(const void __iomem *addr) +{ + return ioread16(addr); +} + +static unsigned int r32(const void __iomem *addr) +{ + return ioread32(addr); +} + static int sh_clk_mstp_enable(struct clk *clk) { sh_clk_write(sh_clk_read(clk) & ~(1 << clk->enable_bit), clk); + if (clk->status_reg) { + unsigned int (*read)(const void __iomem *addr); + int i; + void __iomem *mapped_status = (phys_addr_t)clk->status_reg - + (phys_addr_t)clk->enable_reg + clk->mapped_reg; + + if (clk->flags & CLK_ENABLE_REG_8BIT) + read = r8; + else if (clk->flags & CLK_ENABLE_REG_16BIT) + read = r16; + else + read = r32; + + for (i = 1000; + (read(mapped_status) & (1 << clk->enable_bit)) && i; + i--) + cpu_relax(); + if (!i) { + pr_err("cpg: failed to enable %p[%d]\n", + clk->enable_reg, clk->enable_bit); + return -ETIMEDOUT; + } + } return 0; } |