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author | Imre Deak <imre.deak@intel.com> | 2013-11-25 17:15:29 +0200 |
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committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-11-26 20:04:59 +0100 |
commit | c1ca727f89450cbc560af93045d57a186b83b0dc (patch) | |
tree | b06bab5a952b0d16fed0f280898ed141edcb08e2 /drivers/gpu/drm/exynos/regs-vp.h | |
parent | fbeeaa2306fcff7614c8b41b420a400503b6d28e (diff) | |
download | kernel-common-c1ca727f89450cbc560af93045d57a186b83b0dc.tar.gz kernel-common-c1ca727f89450cbc560af93045d57a186b83b0dc.tar.bz2 kernel-common-c1ca727f89450cbc560af93045d57a186b83b0dc.zip |
drm/i915: support for multiple power wells
HW generations so far had only one always-on power well and optionally
one dynamic power well. Upcoming HW gens may have multiple dynamic power
wells, so add some infrastructure to support them.
The idea is to keep the existing power domain API used by the rest of
the driver and create a mapping between these power domains and the
underlying power wells. This mapping can differ from one HW to another
but high level driver code doesn't need to know about this. Through the
existing get/put API it would just ask for a given power domain and the
power domain framework would make sure the relevant power wells get
enabled in the right order.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Paulo Zanoni <paulo.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/exynos/regs-vp.h')
0 files changed, 0 insertions, 0 deletions