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authorStephen Warren <swarren@wwwdotorg.org>2012-09-27 21:54:21 -0600
committerStephen Warren <swarren@wwwdotorg.org>2012-10-25 20:42:51 -0600
commit805504abdc73cfc745a5fee3d616cdb24bb2a68c (patch)
treeb531ce1bcc94b540d783b8153f90567dd3c735cc /arch/arm/boot/dts/bcm2835.dtsi
parentd0f1c7ffaa32bdda2d413d2db41c51bbdd105834 (diff)
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ARM: bcm2835: enable GPIO/pinctrl
Enable GPIO and pinctrl in Kconfig. Add required <mach/gpio.h> for gpiolib. Instantiate the BCM2835 GPIO module in bcm2835.dtsi. Add a pinctrl definition to bcm2835-rpi-b.dts that sets up all of the board's required pinmux configuration. GPIO aren't specified; that's left to gpio_request(). Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Acked-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/bcm2835.dtsi')
-rw-r--r--arch/arm/boot/dts/bcm2835.dtsi23
1 files changed, 23 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi
index 5c5cbafed191..8917550fd1bb 100644
--- a/arch/arm/boot/dts/bcm2835.dtsi
+++ b/arch/arm/boot/dts/bcm2835.dtsi
@@ -40,5 +40,28 @@
interrupts = <2 25>;
clock-frequency = <3000000>;
};
+
+ gpio: gpio {
+ compatible = "brcm,bcm2835-gpio";
+ reg = <0x7e200000 0xb4>;
+ /*
+ * The GPIO IP block is designed for 3 banks of GPIOs.
+ * Each bank has a GPIO interrupt for itself.
+ * There is an overall "any bank" interrupt.
+ * In order, these are GIC interrupts 17, 18, 19, 20.
+ * Since the BCM2835 only has 2 banks, the 2nd bank
+ * interrupt output appears to be mirrored onto the
+ * 3rd bank's interrupt signal.
+ * So, a bank0 interrupt shows up on 17, 20, and
+ * a bank1 interrupt shows up on 18, 19, 20!
+ */
+ interrupts = <2 17>, <2 18>, <2 19>, <2 20>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
};
};