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| author | Ezequiel Garcia <ezequiel.garcia@free-electrons.com> | 2013-07-26 10:18:00 -0300 |
|---|---|---|
| committer | Jason Cooper <jason@lakedaemon.net> | 2013-08-06 14:11:27 +0000 |
| commit | 14fd8ed0a7fd199131425fe9e802173c4ba6a4e9 (patch) | |
| tree | db73d939f2487613d91c778ec197d4f27f589a22 /arch/arm/boot/dts/armada-370-mirabox.dts | |
| parent | de1af8d486ae05922efbb69b93b902b197dfaca9 (diff) | |
| download | kernel-common-14fd8ed0a7fd199131425fe9e802173c4ba6a4e9.tar.gz kernel-common-14fd8ed0a7fd199131425fe9e802173c4ba6a4e9.tar.bz2 kernel-common-14fd8ed0a7fd199131425fe9e802173c4ba6a4e9.zip | |
ARM: mvebu: Relocate Armada 370/XP PCIe device tree nodes
Now that mbus has been added to the device tree, it's possible to
move the PCIe nodes out of internal registers, placing it directly
below the mbus. This is a more accurate representation of the
hardware.
Moving the PCIe nodes, we now need to introduce an extra cell to
encode the window target ID and attribute. Since this depends on
the PCIe port, we split the ranges translation entries, to correspond
to each MBus window.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Diffstat (limited to 'arch/arm/boot/dts/armada-370-mirabox.dts')
| -rw-r--r-- | arch/arm/boot/dts/armada-370-mirabox.dts | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts index 19341d26f7a3..2471d9da767b 100644 --- a/arch/arm/boot/dts/armada-370-mirabox.dts +++ b/arch/arm/boot/dts/armada-370-mirabox.dts @@ -28,6 +28,22 @@ ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000 MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>; + pcie-controller { + status = "okay"; + + /* Internal mini-PCIe connector */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + + /* Connected on the PCB to a USB 3.0 XHCI controller */ + pcie@2,0 { + /* Port 1, Lane 0 */ + status = "okay"; + }; + }; + internal-regs { serial@12000 { clock-frequency = <200000000>; @@ -123,22 +139,6 @@ reg = <0x25>; }; }; - - pcie-controller { - status = "okay"; - - /* Internal mini-PCIe connector */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - /* Connected on the PCB to a USB 3.0 XHCI controller */ - pcie@2,0 { - /* Port 1, Lane 0 */ - status = "okay"; - }; - }; }; }; }; |