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authorAnas Nashif <anas.nashif@intel.com>2012-11-06 21:16:29 -0800
committerAnas Nashif <anas.nashif@intel.com>2012-11-06 21:16:29 -0800
commit1501461b978a770b6fc8883901d6c3d177661667 (patch)
tree476568764b15008dce7c60e818480d3e5432e176 /src/render_program/exa_wm_write.g7a
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Imported Upstream version 2.20.10upstream/2.20.10
Diffstat (limited to 'src/render_program/exa_wm_write.g7a')
-rw-r--r--src/render_program/exa_wm_write.g7a41
1 files changed, 41 insertions, 0 deletions
diff --git a/src/render_program/exa_wm_write.g7a b/src/render_program/exa_wm_write.g7a
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+++ b/src/render_program/exa_wm_write.g7a
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+/*
+ * Copyright © 2010 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+include(`exa_wm.g4i')
+
+/*
+ * Prepare data in g66-g67 for Red channel, g68-g69 for Green channel,
+ * g70-g71 for Blue and g72-g73 for Alpha channel
+ */
+define(`slot_r_00', `g66')
+define(`slot_r_01', `g67')
+define(`slot_g_00', `g68')
+define(`slot_g_01', `g69')
+define(`slot_b_00', `g70')
+define(`slot_b_01', `g71')
+define(`slot_a_00', `g72')
+define(`slot_a_01', `g73')
+define(`data_port_msg_2_ind', `66')
+
+include(`exa_wm_write.g6i')