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author | Chris Wilson <chris@chris-wilson.co.uk> | 2012-12-21 10:40:47 +0000 |
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committer | Chris Wilson <chris@chris-wilson.co.uk> | 2012-12-21 10:40:47 +0000 |
commit | 347c5a7b33729f1bedd408d2ef24756d51b66f1d (patch) | |
tree | 2b4562434340a9f6f840c5f4dbb66b6e43be0882 | |
parent | 8a67d3f808fcc7c8c51553b1703e8312f28b87a1 (diff) | |
download | xf86-video-intel-347c5a7b33729f1bedd408d2ef24756d51b66f1d.tar.gz xf86-video-intel-347c5a7b33729f1bedd408d2ef24756d51b66f1d.tar.bz2 xf86-video-intel-347c5a7b33729f1bedd408d2ef24756d51b66f1d.zip |
sna/dri: Refactor get_current_msc between blit/flip paths
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
-rw-r--r-- | src/sna/sna_dri.c | 57 |
1 files changed, 29 insertions, 28 deletions
diff --git a/src/sna/sna_dri.c b/src/sna/sna_dri.c index fd5e3de3c..10b6360c8 100644 --- a/src/sna/sna_dri.c +++ b/src/sna/sna_dri.c @@ -1710,6 +1710,24 @@ sna_dri_page_flip_handler(struct sna *sna, sna_dri_flip_event(sna, info); } +static CARD64 +get_current_msc_for_target(struct sna *sna, CARD64 target_msc, int pipe) +{ + CARD64 ret = -1; + + if (target_msc && (sna->flags & SNA_NO_WAIT) == 0) { + drmVBlank vbl; + + VG_CLEAR(vbl); + vbl.request.type = DRM_VBLANK_RELATIVE | pipe_select(pipe); + vbl.request.sequence = 0; + if (sna_wait_vblank(sna, &vbl) == 0) + ret = vbl.reply.sequence; + } + + return ret; +} + static bool sna_dri_schedule_flip(ClientPtr client, DrawablePtr draw, DRI2BufferPtr front, DRI2BufferPtr back, CARD64 *target_msc, CARD64 divisor, @@ -1741,19 +1759,11 @@ sna_dri_schedule_flip(ClientPtr client, DrawablePtr draw, DRI2BufferPtr front, return false; } - /* Get current count */ - if (*target_msc) { - vbl.request.type = DRM_VBLANK_RELATIVE | pipe_select(pipe); - vbl.request.sequence = 0; - if (sna_wait_vblank(sna, &vbl)) - return false; - current_msc = vbl.reply.sequence; - } else - current_msc = 0; + current_msc = get_current_msc_for_target(sna, *target_msc, pipe); + + DBG(("%s: target_msc=%u, current_msc=%u, divisor=%u\n", __FUNCTION__, + (uint32_t)*target_msc, (uint32_t)current_msc, (uint32_t)divisor)); - /* Truncate to match kernel interfaces; means occasional overflow - * misses, but that's generally not a big deal */ - divisor &= 0xffffffff; if (divisor == 0 && current_msc >= *target_msc) { DBG(("%s: performing immediate swap on pipe %d, pending? %d\n", __FUNCTION__, pipe, sna->dri.flip_pending != NULL)); @@ -2032,6 +2042,12 @@ sna_dri_schedule_swap(ClientPtr client, DrawablePtr draw, DRI2BufferPtr front, (long long)divisor, (long long)remainder)); + /* Truncate to match kernel interfaces; means occasional overflow + * misses, but that's generally not a big deal */ + *target_msc &= 0xffffffff; + divisor &= 0xffffffff; + remainder &= 0xffffffff; + if (can_flip(sna, draw, front, back)) { DBG(("%s: try flip\n", __FUNCTION__)); if (sna_dri_schedule_flip(client, draw, front, back, @@ -2058,12 +2074,6 @@ sna_dri_schedule_swap(ClientPtr client, DrawablePtr draw, DRI2BufferPtr front, VG_CLEAR(vbl); - /* Truncate to match kernel interfaces; means occasional overflow - * misses, but that's generally not a big deal */ - *target_msc &= 0xffffffff; - divisor &= 0xffffffff; - remainder &= 0xffffffff; - info = calloc(1, sizeof(struct sna_dri_frame_event)); if (!info) goto blit_fallback; @@ -2082,16 +2092,7 @@ sna_dri_schedule_swap(ClientPtr client, DrawablePtr draw, DRI2BufferPtr front, info->type = swap_type; - if (*target_msc && (sna->flags & SNA_NO_WAIT) == 0) { - /* Get current count */ - vbl.request.type = DRM_VBLANK_RELATIVE | pipe_select(pipe); - vbl.request.sequence = 0; - if (sna_wait_vblank(sna, &vbl)) - goto blit_fallback; - current_msc = vbl.reply.sequence; - } else - current_msc = -1; - + current_msc = get_current_msc_for_target(sna, *target_msc, pipe); DBG(("%s: target_msc=%u, current_msc=%u, divisor=%u\n", __FUNCTION__, (uint32_t)*target_msc, (uint32_t)current_msc, (uint32_t)divisor)); |