diff options
Diffstat (limited to 'tcg/s390/tcg-target.c')
| -rw-r--r-- | tcg/s390/tcg-target.c | 129 |
1 files changed, 19 insertions, 110 deletions
diff --git a/tcg/s390/tcg-target.c b/tcg/s390/tcg-target.c index f229f1c34..907d9d174 100644 --- a/tcg/s390/tcg-target.c +++ b/tcg/s390/tcg-target.c @@ -24,11 +24,15 @@ * THE SOFTWARE. */ +#include "tcg-be-null.h" + /* We only support generating code for 64-bit mode. */ #if TCG_TARGET_REG_BITS != 64 #error "unsupported code generation mode" #endif +#include "elf.h" + /* ??? The translation blocks produced by TCG are generally small enough to be entirely reachable with a 16-bit displacement. Leaving the option for a 32-bit displacement here Just In Case. */ @@ -315,9 +319,6 @@ static const uint8_t tcg_cond_to_ltr_cond[] = { }; #ifdef CONFIG_SOFTMMU - -#include "exec/softmmu_defs.h" - /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr, int mmu_idx) */ static const void * const qemu_ld_helpers[4] = { @@ -351,10 +352,10 @@ static uint8_t *tb_ret_addr; static uint64_t facilities; static void patch_reloc(uint8_t *code_ptr, int type, - tcg_target_long value, tcg_target_long addend) + intptr_t value, intptr_t addend) { - tcg_target_long code_ptr_tl = (tcg_target_long)code_ptr; - tcg_target_long pcrel2; + intptr_t code_ptr_tl = (intptr_t)code_ptr; + intptr_t pcrel2; /* ??? Not the usual definition of "addend". */ pcrel2 = (value - (code_ptr_tl + addend)) >> 1; @@ -771,7 +772,7 @@ static void tcg_out_mem(TCGContext *s, S390Opcode opc_rx, S390Opcode opc_rxy, /* load data without address translation or endianness conversion */ static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg data, - TCGReg base, tcg_target_long ofs) + TCGReg base, intptr_t ofs) { if (type == TCG_TYPE_I32) { tcg_out_mem(s, RX_L, RXY_LY, data, base, TCG_REG_NONE, ofs); @@ -781,7 +782,7 @@ static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg data, } static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg data, - TCGReg base, tcg_target_long ofs) + TCGReg base, intptr_t ofs) { if (type == TCG_TYPE_I32) { tcg_out_mem(s, RX_ST, RXY_STY, data, base, TCG_REG_NONE, ofs); @@ -2213,112 +2214,20 @@ static const TCGTargetOpDef s390_op_defs[] = { { -1 }, }; -/* ??? Linux kernels provide an AUXV entry AT_HWCAP that provides most of - this information. However, getting at that entry is not easy this far - away from main. Our options are: start searching from environ, but - that fails as soon as someone does a setenv in between. Read the data - from /proc/self/auxv. Or do the probing ourselves. The only thing - extra that AT_HWCAP gives us is HWCAP_S390_HIGH_GPRS, which indicates - that the kernel saves all 64-bits of the registers around traps while - in 31-bit mode. But this is true of all "recent" kernels (ought to dig - back and see from when this might not be true). */ - -#include <signal.h> - -static volatile sig_atomic_t got_sigill; - -static void sigill_handler(int sig) -{ - got_sigill = 1; -} - static void query_facilities(void) { - struct sigaction sa_old, sa_new; - register int r0 __asm__("0"); - register void *r1 __asm__("1"); - int fail; - - memset(&sa_new, 0, sizeof(sa_new)); - sa_new.sa_handler = sigill_handler; - sigaction(SIGILL, &sa_new, &sa_old); - - /* First, try STORE FACILITY LIST EXTENDED. If this is present, then - we need not do any more probing. Unfortunately, this itself is an - extension and the original STORE FACILITY LIST instruction is - kernel-only, storing its results at absolute address 200. */ - /* stfle 0(%r1) */ - r1 = &facilities; - asm volatile(".word 0xb2b0,0x1000" - : "=r"(r0) : "0"(0), "r"(r1) : "memory", "cc"); - - if (got_sigill) { - /* STORE FACILITY EXTENDED is not available. Probe for one of each - kind of instruction that we're interested in. */ - /* ??? Possibly some of these are in practice never present unless - the store-facility-extended facility is also present. But since - that isn't documented it's just better to probe for each. */ - - /* Test for z/Architecture. Required even in 31-bit mode. */ - got_sigill = 0; - /* agr %r0,%r0 */ - asm volatile(".word 0xb908,0x0000" : "=r"(r0) : : "cc"); - if (!got_sigill) { - facilities |= FACILITY_ZARCH_ACTIVE; - } - - /* Test for long displacement. */ - got_sigill = 0; - /* ly %r0,0(%r1) */ - r1 = &facilities; - asm volatile(".word 0xe300,0x1000,0x0058" - : "=r"(r0) : "r"(r1) : "cc"); - if (!got_sigill) { - facilities |= FACILITY_LONG_DISP; - } + unsigned long hwcap = qemu_getauxval(AT_HWCAP); - /* Test for extended immediates. */ - got_sigill = 0; - /* afi %r0,0 */ - asm volatile(".word 0xc209,0x0000,0x0000" : : : "cc"); - if (!got_sigill) { - facilities |= FACILITY_EXT_IMM; - } - - /* Test for general-instructions-extension. */ - got_sigill = 0; - /* msfi %r0,1 */ - asm volatile(".word 0xc201,0x0000,0x0001"); - if (!got_sigill) { - facilities |= FACILITY_GEN_INST_EXT; - } - } - - sigaction(SIGILL, &sa_old, NULL); + /* Is STORE FACILITY LIST EXTENDED available? Honestly, I believe this + is present on all 64-bit systems, but let's check for it anyway. */ + if (hwcap & HWCAP_S390_STFLE) { + register int r0 __asm__("0"); + register void *r1 __asm__("1"); - /* The translator currently uses these extensions unconditionally. - Pruning this back to the base ESA/390 architecture doesn't seem - worthwhile, since even the KVM target requires z/Arch. */ - fail = 0; - if ((facilities & FACILITY_ZARCH_ACTIVE) == 0) { - fprintf(stderr, "TCG: z/Arch facility is required.\n"); - fprintf(stderr, "TCG: Boot with a 64-bit enabled kernel.\n"); - fail = 1; - } - if ((facilities & FACILITY_LONG_DISP) == 0) { - fprintf(stderr, "TCG: long-displacement facility is required.\n"); - fail = 1; - } - - /* So far there's just enough support for 31-bit mode to let the - compile succeed. This is good enough to run QEMU with KVM. */ - if (sizeof(void *) != 8) { - fprintf(stderr, "TCG: 31-bit mode is not supported.\n"); - fail = 1; - } - - if (fail) { - exit(-1); + /* stfle 0(%r1) */ + r1 = &facilities; + asm volatile(".word 0xb2b0,0x1000" + : "=r"(r0) : "0"(0), "r"(r1) : "memory", "cc"); } } |