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-rw-r--r--hw/display/Makefile.objs2
-rw-r--r--hw/display/ads7846.c5
-rw-r--r--hw/display/bcm2835_fb.c1
-rw-r--r--hw/display/blizzard.c120
-rw-r--r--hw/display/blizzard_template.h146
-rw-r--r--hw/display/cg3.c2
-rw-r--r--hw/display/dpcd.c173
-rw-r--r--hw/display/exynos4210_fimd.c19
-rw-r--r--hw/display/jazz_led.c18
-rw-r--r--hw/display/milkymist-tmu2.c27
-rw-r--r--hw/display/milkymist-vgafb.c18
-rw-r--r--hw/display/omap_lcd_template.h10
-rw-r--r--hw/display/omap_lcdc.c48
-rw-r--r--hw/display/pl110.c1
-rw-r--r--hw/display/qxl.c127
-rw-r--r--hw/display/qxl.h9
-rw-r--r--hw/display/ssd0323.c5
-rw-r--r--hw/display/tc6393xb.c1
-rw-r--r--hw/display/trace-events122
-rw-r--r--hw/display/vga.c4
-rw-r--r--hw/display/vga.h6
-rw-r--r--hw/display/vga_int.h5
-rw-r--r--hw/display/virtio-gpu-3d.c14
-rw-r--r--hw/display/virtio-gpu-pci.c4
-rw-r--r--hw/display/virtio-gpu.c251
-rw-r--r--hw/display/virtio-vga.c24
-rw-r--r--hw/display/xenfb.c5
-rw-r--r--hw/display/xlnx_dp.c1338
28 files changed, 372 insertions, 2133 deletions
diff --git a/hw/display/Makefile.objs b/hw/display/Makefile.objs
index 063889bea..d99780eeb 100644
--- a/hw/display/Makefile.objs
+++ b/hw/display/Makefile.objs
@@ -43,5 +43,3 @@ virtio-gpu.o-cflags := $(VIRGL_CFLAGS)
virtio-gpu.o-libs += $(VIRGL_LIBS)
virtio-gpu-3d.o-cflags := $(VIRGL_CFLAGS)
virtio-gpu-3d.o-libs += $(VIRGL_LIBS)
-obj-$(CONFIG_DPCD) += dpcd.o
-obj-$(CONFIG_XLNX_ZYNQMP) += xlnx_dp.o
diff --git a/hw/display/ads7846.c b/hw/display/ads7846.c
index 166edade7..05aa2d1e6 100644
--- a/hw/display/ads7846.c
+++ b/hw/display/ads7846.c
@@ -133,7 +133,7 @@ static const VMStateDescription vmstate_ads7846 = {
}
};
-static void ads7846_realize(SSISlave *d, Error **errp)
+static int ads7846_init(SSISlave *d)
{
DeviceState *dev = DEVICE(d);
ADS7846State *s = FROM_SSI_SLAVE(ADS7846State, d);
@@ -152,13 +152,14 @@ static void ads7846_realize(SSISlave *d, Error **errp)
ads7846_int_update(s);
vmstate_register(NULL, -1, &vmstate_ads7846, s);
+ return 0;
}
static void ads7846_class_init(ObjectClass *klass, void *data)
{
SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
- k->realize = ads7846_realize;
+ k->init = ads7846_init;
k->transfer = ads7846_transfer;
}
diff --git a/hw/display/bcm2835_fb.c b/hw/display/bcm2835_fb.c
index 7eab92765..506f1d3d9 100644
--- a/hw/display/bcm2835_fb.c
+++ b/hw/display/bcm2835_fb.c
@@ -29,7 +29,6 @@
#include "hw/display/framebuffer.h"
#include "ui/pixel_ops.h"
#include "hw/misc/bcm2835_mbox_defs.h"
-#include "qemu/log.h"
#define DEFAULT_VCRAM_SIZE 0x4000000
#define BCM2835_FB_OFFSET 0x00100000
diff --git a/hw/display/blizzard.c b/hw/display/blizzard.c
index cbf07d14d..c231960d9 100644
--- a/hw/display/blizzard.c
+++ b/hw/display/blizzard.c
@@ -925,83 +925,16 @@ static void blizzard_update_display(void *opaque)
s->my[1] = 0;
}
-static void blizzard_draw_line16_32(uint32_t *dest,
- const uint16_t *src, unsigned int width)
-{
- uint16_t data;
- unsigned int r, g, b;
- const uint16_t *end = (const void *) src + width;
- while (src < end) {
- data = *src ++;
- b = (data & 0x1f) << 3;
- data >>= 5;
- g = (data & 0x3f) << 2;
- data >>= 6;
- r = (data & 0x1f) << 3;
- data >>= 5;
- *dest++ = rgb_to_pixel32(r, g, b);
- }
-}
-
-static void blizzard_draw_line24mode1_32(uint32_t *dest,
- const uint8_t *src, unsigned int width)
-{
- /* TODO: check if SDL 24-bit planes are not in the same format and
- * if so, use memcpy */
- unsigned int r[2], g[2], b[2];
- const uint8_t *end = src + width;
- while (src < end) {
- g[0] = *src ++;
- r[0] = *src ++;
- r[1] = *src ++;
- b[0] = *src ++;
- *dest++ = rgb_to_pixel32(r[0], g[0], b[0]);
- b[1] = *src ++;
- g[1] = *src ++;
- *dest++ = rgb_to_pixel32(r[1], g[1], b[1]);
- }
-}
-
-static void blizzard_draw_line24mode2_32(uint32_t *dest,
- const uint8_t *src, unsigned int width)
-{
- unsigned int r, g, b;
- const uint8_t *end = src + width;
- while (src < end) {
- r = *src ++;
- src ++;
- b = *src ++;
- g = *src ++;
- *dest++ = rgb_to_pixel32(r, g, b);
- }
-}
-
-/* No rotation */
-static blizzard_fn_t blizzard_draw_fn_32[0x10] = {
- NULL,
- /* RGB 5:6:5*/
- (blizzard_fn_t) blizzard_draw_line16_32,
- /* RGB 6:6:6 mode 1 */
- (blizzard_fn_t) blizzard_draw_line24mode1_32,
- /* RGB 8:8:8 mode 1 */
- (blizzard_fn_t) blizzard_draw_line24mode1_32,
- NULL, NULL,
- /* RGB 6:6:6 mode 2 */
- (blizzard_fn_t) blizzard_draw_line24mode2_32,
- /* RGB 8:8:8 mode 2 */
- (blizzard_fn_t) blizzard_draw_line24mode2_32,
- /* YUV 4:2:2 */
- NULL,
- /* YUV 4:2:0 */
- NULL,
- NULL, NULL, NULL, NULL, NULL, NULL,
-};
-
-/* 90deg, 180deg and 270deg rotation */
-static blizzard_fn_t blizzard_draw_fn_r_32[0x10] = {
- /* TODO */
- [0 ... 0xf] = NULL,
-};
+#define DEPTH 8
+#include "blizzard_template.h"
+#define DEPTH 15
+#include "blizzard_template.h"
+#define DEPTH 16
+#include "blizzard_template.h"
+#define DEPTH 24
+#include "blizzard_template.h"
+#define DEPTH 32
+#include "blizzard_template.h"
static const GraphicHwOps blizzard_ops = {
.invalidate = blizzard_invalidate_display,
@@ -1018,10 +951,35 @@ void *s1d13745_init(qemu_irq gpio_int)
s->con = graphic_console_init(NULL, 0, &blizzard_ops, s);
surface = qemu_console_surface(s->con);
- assert(surface_bits_per_pixel(surface) == 32);
-
- s->line_fn_tab[0] = blizzard_draw_fn_32;
- s->line_fn_tab[1] = blizzard_draw_fn_r_32;
+ switch (surface_bits_per_pixel(surface)) {
+ case 0:
+ s->line_fn_tab[0] = s->line_fn_tab[1] =
+ g_malloc0(sizeof(blizzard_fn_t) * 0x10);
+ break;
+ case 8:
+ s->line_fn_tab[0] = blizzard_draw_fn_8;
+ s->line_fn_tab[1] = blizzard_draw_fn_r_8;
+ break;
+ case 15:
+ s->line_fn_tab[0] = blizzard_draw_fn_15;
+ s->line_fn_tab[1] = blizzard_draw_fn_r_15;
+ break;
+ case 16:
+ s->line_fn_tab[0] = blizzard_draw_fn_16;
+ s->line_fn_tab[1] = blizzard_draw_fn_r_16;
+ break;
+ case 24:
+ s->line_fn_tab[0] = blizzard_draw_fn_24;
+ s->line_fn_tab[1] = blizzard_draw_fn_r_24;
+ break;
+ case 32:
+ s->line_fn_tab[0] = blizzard_draw_fn_32;
+ s->line_fn_tab[1] = blizzard_draw_fn_r_32;
+ break;
+ default:
+ fprintf(stderr, "%s: Bad color depth\n", __FUNCTION__);
+ exit(1);
+ }
blizzard_reset(s);
diff --git a/hw/display/blizzard_template.h b/hw/display/blizzard_template.h
new file mode 100644
index 000000000..b7ef27c80
--- /dev/null
+++ b/hw/display/blizzard_template.h
@@ -0,0 +1,146 @@
+/*
+ * QEMU Epson S1D13744/S1D13745 templates
+ *
+ * Copyright (C) 2008 Nokia Corporation
+ * Written by Andrzej Zaborowski <andrew@openedhand.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 or
+ * (at your option) version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#define SKIP_PIXEL(to) (to += deststep)
+#if DEPTH == 8
+# define PIXEL_TYPE uint8_t
+# define COPY_PIXEL(to, from) do { *to = from; SKIP_PIXEL(to); } while (0)
+# define COPY_PIXEL1(to, from) (*to++ = from)
+#elif DEPTH == 15 || DEPTH == 16
+# define PIXEL_TYPE uint16_t
+# define COPY_PIXEL(to, from) do { *to = from; SKIP_PIXEL(to); } while (0)
+# define COPY_PIXEL1(to, from) (*to++ = from)
+#elif DEPTH == 24
+# define PIXEL_TYPE uint8_t
+# define COPY_PIXEL(to, from) \
+ do { \
+ to[0] = from; \
+ to[1] = (from) >> 8; \
+ to[2] = (from) >> 16; \
+ SKIP_PIXEL(to); \
+ } while (0)
+
+# define COPY_PIXEL1(to, from) \
+ do { \
+ *to++ = from; \
+ *to++ = (from) >> 8; \
+ *to++ = (from) >> 16; \
+ } while (0)
+#elif DEPTH == 32
+# define PIXEL_TYPE uint32_t
+# define COPY_PIXEL(to, from) do { *to = from; SKIP_PIXEL(to); } while (0)
+# define COPY_PIXEL1(to, from) (*to++ = from)
+#else
+# error unknown bit depth
+#endif
+
+#ifdef HOST_WORDS_BIGENDIAN
+# define SWAP_WORDS 1
+#endif
+
+static void glue(blizzard_draw_line16_, DEPTH)(PIXEL_TYPE *dest,
+ const uint16_t *src, unsigned int width)
+{
+#if !defined(SWAP_WORDS) && DEPTH == 16
+ memcpy(dest, src, width);
+#else
+ uint16_t data;
+ unsigned int r, g, b;
+ const uint16_t *end = (const void *) src + width;
+ while (src < end) {
+ data = *src ++;
+ b = (data & 0x1f) << 3;
+ data >>= 5;
+ g = (data & 0x3f) << 2;
+ data >>= 6;
+ r = (data & 0x1f) << 3;
+ data >>= 5;
+ COPY_PIXEL1(dest, glue(rgb_to_pixel, DEPTH)(r, g, b));
+ }
+#endif
+}
+
+static void glue(blizzard_draw_line24mode1_, DEPTH)(PIXEL_TYPE *dest,
+ const uint8_t *src, unsigned int width)
+{
+ /* TODO: check if SDL 24-bit planes are not in the same format and
+ * if so, use memcpy */
+ unsigned int r[2], g[2], b[2];
+ const uint8_t *end = src + width;
+ while (src < end) {
+ g[0] = *src ++;
+ r[0] = *src ++;
+ r[1] = *src ++;
+ b[0] = *src ++;
+ COPY_PIXEL1(dest, glue(rgb_to_pixel, DEPTH)(r[0], g[0], b[0]));
+ b[1] = *src ++;
+ g[1] = *src ++;
+ COPY_PIXEL1(dest, glue(rgb_to_pixel, DEPTH)(r[1], g[1], b[1]));
+ }
+}
+
+static void glue(blizzard_draw_line24mode2_, DEPTH)(PIXEL_TYPE *dest,
+ const uint8_t *src, unsigned int width)
+{
+ unsigned int r, g, b;
+ const uint8_t *end = src + width;
+ while (src < end) {
+ r = *src ++;
+ src ++;
+ b = *src ++;
+ g = *src ++;
+ COPY_PIXEL1(dest, glue(rgb_to_pixel, DEPTH)(r, g, b));
+ }
+}
+
+/* No rotation */
+static blizzard_fn_t glue(blizzard_draw_fn_, DEPTH)[0x10] = {
+ NULL,
+ /* RGB 5:6:5*/
+ (blizzard_fn_t) glue(blizzard_draw_line16_, DEPTH),
+ /* RGB 6:6:6 mode 1 */
+ (blizzard_fn_t) glue(blizzard_draw_line24mode1_, DEPTH),
+ /* RGB 8:8:8 mode 1 */
+ (blizzard_fn_t) glue(blizzard_draw_line24mode1_, DEPTH),
+ NULL, NULL,
+ /* RGB 6:6:6 mode 2 */
+ (blizzard_fn_t) glue(blizzard_draw_line24mode2_, DEPTH),
+ /* RGB 8:8:8 mode 2 */
+ (blizzard_fn_t) glue(blizzard_draw_line24mode2_, DEPTH),
+ /* YUV 4:2:2 */
+ NULL,
+ /* YUV 4:2:0 */
+ NULL,
+ NULL, NULL, NULL, NULL, NULL, NULL,
+};
+
+/* 90deg, 180deg and 270deg rotation */
+static blizzard_fn_t glue(blizzard_draw_fn_r_, DEPTH)[0x10] = {
+ /* TODO */
+ [0 ... 0xf] = NULL,
+};
+
+#undef DEPTH
+#undef SKIP_PIXEL
+#undef COPY_PIXEL
+#undef COPY_PIXEL1
+#undef PIXEL_TYPE
+
+#undef SWAP_WORDS
diff --git a/hw/display/cg3.c b/hw/display/cg3.c
index 117422039..fc0d97fa4 100644
--- a/hw/display/cg3.c
+++ b/hw/display/cg3.c
@@ -26,12 +26,10 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qemu-common.h"
-#include "cpu.h"
#include "qemu/error-report.h"
#include "ui/console.h"
#include "hw/sysbus.h"
#include "hw/loader.h"
-#include "qemu/log.h"
/* Change to 1 to enable debugging */
#define DEBUG_CG3 0
diff --git a/hw/display/dpcd.c b/hw/display/dpcd.c
deleted file mode 100644
index ce92ff6e2..000000000
--- a/hw/display/dpcd.c
+++ /dev/null
@@ -1,173 +0,0 @@
-/*
- * dpcd.c
- *
- * Copyright (C) 2015 : GreenSocs Ltd
- * http://www.greensocs.com/ , email: info@greensocs.com
- *
- * Developed by :
- * Frederic Konrad <fred.konrad@greensocs.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 2 of the License, or
- * (at your option)any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, see <http://www.gnu.org/licenses/>.
- *
- */
-
-/*
- * This is a simple AUX slave which emulates a connected screen.
- */
-
-#include "qemu/osdep.h"
-#include "qemu/log.h"
-#include "hw/misc/auxbus.h"
-#include "hw/display/dpcd.h"
-
-#ifndef DEBUG_DPCD
-#define DEBUG_DPCD 0
-#endif
-
-#define DPRINTF(fmt, ...) do { \
- if (DEBUG_DPCD) { \
- qemu_log("dpcd: " fmt, ## __VA_ARGS__); \
- } \
-} while (0);
-
-#define DPCD_READABLE_AREA 0x600
-
-struct DPCDState {
- /*< private >*/
- AUXSlave parent_obj;
-
- /*< public >*/
- /*
- * The DCPD is 0x7FFFF length but read as 0 after offset 0x5FF.
- */
- uint8_t dpcd_info[DPCD_READABLE_AREA];
-
- MemoryRegion iomem;
-};
-
-static uint64_t dpcd_read(void *opaque, hwaddr offset, unsigned size)
-{
- uint8_t ret;
- DPCDState *e = DPCD(opaque);
-
- if (offset < DPCD_READABLE_AREA) {
- ret = e->dpcd_info[offset];
- } else {
- qemu_log_mask(LOG_GUEST_ERROR, "dpcd: Bad offset 0x%" HWADDR_PRIX "\n",
- offset);
- ret = 0;
- }
-
- DPRINTF("read 0x%" PRIX8 " @0x%" HWADDR_PRIX "\n", ret, offset);
- return ret;
-}
-
-static void dpcd_write(void *opaque, hwaddr offset, uint64_t value,
- unsigned size)
-{
- DPCDState *e = DPCD(opaque);
-
- DPRINTF("write 0x%" PRIX8 " @0x%" HWADDR_PRIX "\n", (uint8_t)value, offset);
-
- if (offset < DPCD_READABLE_AREA) {
- e->dpcd_info[offset] = value;
- } else {
- qemu_log_mask(LOG_GUEST_ERROR, "dpcd: Bad offset 0x%" HWADDR_PRIX "\n",
- offset);
- }
-}
-
-static const MemoryRegionOps aux_ops = {
- .read = dpcd_read,
- .write = dpcd_write,
- .valid = {
- .min_access_size = 1,
- .max_access_size = 1,
- },
- .impl = {
- .min_access_size = 1,
- .max_access_size = 1,
- },
-};
-
-static void dpcd_reset(DeviceState *dev)
-{
- DPCDState *s = DPCD(dev);
-
- memset(&(s->dpcd_info), 0, sizeof(s->dpcd_info));
-
- s->dpcd_info[DPCD_REVISION] = DPCD_REV_1_0;
- s->dpcd_info[DPCD_MAX_LINK_RATE] = DPCD_5_4GBPS;
- s->dpcd_info[DPCD_MAX_LANE_COUNT] = DPCD_FOUR_LANES;
- s->dpcd_info[DPCD_RECEIVE_PORT0_CAP_0] = DPCD_EDID_PRESENT;
- /* buffer size */
- s->dpcd_info[DPCD_RECEIVE_PORT0_CAP_1] = 0xFF;
-
- s->dpcd_info[DPCD_LANE0_1_STATUS] = DPCD_LANE0_CR_DONE
- | DPCD_LANE0_CHANNEL_EQ_DONE
- | DPCD_LANE0_SYMBOL_LOCKED
- | DPCD_LANE1_CR_DONE
- | DPCD_LANE1_CHANNEL_EQ_DONE
- | DPCD_LANE1_SYMBOL_LOCKED;
- s->dpcd_info[DPCD_LANE2_3_STATUS] = DPCD_LANE2_CR_DONE
- | DPCD_LANE2_CHANNEL_EQ_DONE
- | DPCD_LANE2_SYMBOL_LOCKED
- | DPCD_LANE3_CR_DONE
- | DPCD_LANE3_CHANNEL_EQ_DONE
- | DPCD_LANE3_SYMBOL_LOCKED;
-
- s->dpcd_info[DPCD_LANE_ALIGN_STATUS_UPDATED] = DPCD_INTERLANE_ALIGN_DONE;
- s->dpcd_info[DPCD_SINK_STATUS] = DPCD_RECEIVE_PORT_0_STATUS;
-}
-
-static void dpcd_init(Object *obj)
-{
- DPCDState *s = DPCD(obj);
-
- memory_region_init_io(&s->iomem, obj, &aux_ops, s, TYPE_DPCD, 0x7FFFF);
- aux_init_mmio(AUX_SLAVE(obj), &s->iomem);
-}
-
-static const VMStateDescription vmstate_dpcd = {
- .name = TYPE_DPCD,
- .version_id = 0,
- .minimum_version_id = 0,
- .fields = (VMStateField[]) {
- VMSTATE_UINT8_ARRAY_V(dpcd_info, DPCDState, DPCD_READABLE_AREA, 0),
- VMSTATE_END_OF_LIST()
- }
-};
-
-static void dpcd_class_init(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
-
- dc->reset = dpcd_reset;
- dc->vmsd = &vmstate_dpcd;
-}
-
-static const TypeInfo dpcd_info = {
- .name = TYPE_DPCD,
- .parent = TYPE_AUX_SLAVE,
- .instance_size = sizeof(DPCDState),
- .class_init = dpcd_class_init,
- .instance_init = dpcd_init,
-};
-
-static void dpcd_register_types(void)
-{
- type_register_static(&dpcd_info);
-}
-
-type_init(dpcd_register_types)
diff --git a/hw/display/exynos4210_fimd.c b/hw/display/exynos4210_fimd.c
index e5be71340..728eb214a 100644
--- a/hw/display/exynos4210_fimd.c
+++ b/hw/display/exynos4210_fimd.c
@@ -1909,10 +1909,9 @@ static const GraphicHwOps exynos4210_fimd_ops = {
.gfx_update = exynos4210_fimd_update,
};
-static void exynos4210_fimd_init(Object *obj)
+static int exynos4210_fimd_init(SysBusDevice *dev)
{
- Exynos4210fimdState *s = EXYNOS4210_FIMD(obj);
- SysBusDevice *dev = SYS_BUS_DEVICE(obj);
+ Exynos4210fimdState *s = EXYNOS4210_FIMD(dev);
s->ifb = NULL;
@@ -1920,32 +1919,28 @@ static void exynos4210_fimd_init(Object *obj)
sysbus_init_irq(dev, &s->irq[1]);
sysbus_init_irq(dev, &s->irq[2]);
- memory_region_init_io(&s->iomem, obj, &exynos4210_fimd_mmio_ops, s,
+ memory_region_init_io(&s->iomem, OBJECT(s), &exynos4210_fimd_mmio_ops, s,
"exynos4210.fimd", FIMD_REGS_SIZE);
sysbus_init_mmio(dev, &s->iomem);
-}
-
-static void exynos4210_fimd_realize(DeviceState *dev, Error **errp)
-{
- Exynos4210fimdState *s = EXYNOS4210_FIMD(dev);
+ s->console = graphic_console_init(DEVICE(dev), 0, &exynos4210_fimd_ops, s);
- s->console = graphic_console_init(dev, 0, &exynos4210_fimd_ops, s);
+ return 0;
}
static void exynos4210_fimd_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+ SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
dc->vmsd = &exynos4210_fimd_vmstate;
dc->reset = exynos4210_fimd_reset;
- dc->realize = exynos4210_fimd_realize;
+ k->init = exynos4210_fimd_init;
}
static const TypeInfo exynos4210_fimd_info = {
.name = TYPE_EXYNOS4210_FIMD,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(Exynos4210fimdState),
- .instance_init = exynos4210_fimd_init,
.class_init = exynos4210_fimd_class_init,
};
diff --git a/hw/display/jazz_led.c b/hw/display/jazz_led.c
index b72fdb171..09dcdb46a 100644
--- a/hw/display/jazz_led.c
+++ b/hw/display/jazz_led.c
@@ -267,20 +267,16 @@ static const GraphicHwOps jazz_led_ops = {
.text_update = jazz_led_text_update,
};
-static void jazz_led_init(Object *obj)
+static int jazz_led_init(SysBusDevice *dev)
{
- LedState *s = JAZZ_LED(obj);
- SysBusDevice *dev = SYS_BUS_DEVICE(obj);
+ LedState *s = JAZZ_LED(dev);
- memory_region_init_io(&s->iomem, obj, &led_ops, s, "led", 1);
+ memory_region_init_io(&s->iomem, OBJECT(s), &led_ops, s, "led", 1);
sysbus_init_mmio(dev, &s->iomem);
-}
-static void jazz_led_realize(DeviceState *dev, Error **errp)
-{
- LedState *s = JAZZ_LED(dev);
+ s->con = graphic_console_init(DEVICE(dev), 0, &jazz_led_ops, s);
- s->con = graphic_console_init(dev, 0, &jazz_led_ops, s);
+ return 0;
}
static void jazz_led_reset(DeviceState *d)
@@ -295,18 +291,18 @@ static void jazz_led_reset(DeviceState *d)
static void jazz_led_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+ SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
+ k->init = jazz_led_init;
dc->desc = "Jazz LED display",
dc->vmsd = &vmstate_jazz_led;
dc->reset = jazz_led_reset;
- dc->realize = jazz_led_realize;
}
static const TypeInfo jazz_led_info = {
.name = TYPE_JAZZ_LED,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(LedState),
- .instance_init = jazz_led_init,
.class_init = jazz_led_class_init,
};
diff --git a/hw/display/milkymist-tmu2.c b/hw/display/milkymist-tmu2.c
index 9c0018448..9bc88f93b 100644
--- a/hw/display/milkymist-tmu2.c
+++ b/hw/display/milkymist-tmu2.c
@@ -20,7 +20,7 @@
*
*
* Specification available at:
- * http://milkymist.walle.cc/socdoc/tmu2.pdf
+ * http://www.milkymist.org/socdoc/tmu2.pdf
*
*/
@@ -29,7 +29,6 @@
#include "hw/sysbus.h"
#include "trace.h"
#include "qemu/error-report.h"
-#include "qapi/error.h"
#include <X11/Xlib.h>
#include <epoxy/gl.h>
@@ -444,25 +443,21 @@ static void milkymist_tmu2_reset(DeviceState *d)
}
}
-static void milkymist_tmu2_init(Object *obj)
+static int milkymist_tmu2_init(SysBusDevice *dev)
{
- MilkymistTMU2State *s = MILKYMIST_TMU2(obj);
- SysBusDevice *dev = SYS_BUS_DEVICE(obj);
+ MilkymistTMU2State *s = MILKYMIST_TMU2(dev);
+
+ if (tmu2_glx_init(s)) {
+ return 1;
+ }
sysbus_init_irq(dev, &s->irq);
- memory_region_init_io(&s->regs_region, obj, &tmu2_mmio_ops, s,
+ memory_region_init_io(&s->regs_region, OBJECT(s), &tmu2_mmio_ops, s,
"milkymist-tmu2", R_MAX * 4);
sysbus_init_mmio(dev, &s->regs_region);
-}
-static void milkymist_tmu2_realize(DeviceState *dev, Error **errp)
-{
- MilkymistTMU2State *s = MILKYMIST_TMU2(dev);
-
- if (tmu2_glx_init(s)) {
- error_setg(errp, "tmu2_glx_init failed");
- }
+ return 0;
}
static const VMStateDescription vmstate_milkymist_tmu2 = {
@@ -478,8 +473,9 @@ static const VMStateDescription vmstate_milkymist_tmu2 = {
static void milkymist_tmu2_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+ SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
- dc->realize = milkymist_tmu2_realize;
+ k->init = milkymist_tmu2_init;
dc->reset = milkymist_tmu2_reset;
dc->vmsd = &vmstate_milkymist_tmu2;
}
@@ -488,7 +484,6 @@ static const TypeInfo milkymist_tmu2_info = {
.name = TYPE_MILKYMIST_TMU2,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(MilkymistTMU2State),
- .instance_init = milkymist_tmu2_init,
.class_init = milkymist_tmu2_class_init,
};
diff --git a/hw/display/milkymist-vgafb.c b/hw/display/milkymist-vgafb.c
index 177fdac7d..19ca25647 100644
--- a/hw/display/milkymist-vgafb.c
+++ b/hw/display/milkymist-vgafb.c
@@ -19,7 +19,7 @@
*
*
* Specification available at:
- * http://milkymist.walle.cc/socdoc/vgafb.pdf
+ * http://www.milkymist.org/socdoc/vgafb.pdf
*/
#include "qemu/osdep.h"
@@ -292,21 +292,17 @@ static const GraphicHwOps vgafb_ops = {
.gfx_update = vgafb_update_display,
};
-static void milkymist_vgafb_init(Object *obj)
+static int milkymist_vgafb_init(SysBusDevice *dev)
{
- MilkymistVgafbState *s = MILKYMIST_VGAFB(obj);
- SysBusDevice *dev = SYS_BUS_DEVICE(obj);
+ MilkymistVgafbState *s = MILKYMIST_VGAFB(dev);
memory_region_init_io(&s->regs_region, OBJECT(s), &vgafb_mmio_ops, s,
"milkymist-vgafb", R_MAX * 4);
sysbus_init_mmio(dev, &s->regs_region);
-}
-static void milkymist_vgafb_realize(DeviceState *dev, Error **errp)
-{
- MilkymistVgafbState *s = MILKYMIST_VGAFB(dev);
+ s->con = graphic_console_init(DEVICE(dev), 0, &vgafb_ops, s);
- s->con = graphic_console_init(dev, 0, &vgafb_ops, s);
+ return 0;
}
static int vgafb_post_load(void *opaque, int version_id)
@@ -335,18 +331,18 @@ static Property milkymist_vgafb_properties[] = {
static void milkymist_vgafb_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+ SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
+ k->init = milkymist_vgafb_init;
dc->reset = milkymist_vgafb_reset;
dc->vmsd = &vmstate_milkymist_vgafb;
dc->props = milkymist_vgafb_properties;
- dc->realize = milkymist_vgafb_realize;
}
static const TypeInfo milkymist_vgafb_info = {
.name = TYPE_MILKYMIST_VGAFB,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(MilkymistVgafbState),
- .instance_init = milkymist_vgafb_init,
.class_init = milkymist_vgafb_class_init,
};
diff --git a/hw/display/omap_lcd_template.h b/hw/display/omap_lcd_template.h
index 1025ff382..f0ce71fd6 100644
--- a/hw/display/omap_lcd_template.h
+++ b/hw/display/omap_lcd_template.h
@@ -27,7 +27,13 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#if DEPTH == 32
+#if DEPTH == 8
+# define BPP 1
+# define PIXEL_TYPE uint8_t
+#elif DEPTH == 15 || DEPTH == 16
+# define BPP 2
+# define PIXEL_TYPE uint16_t
+#elif DEPTH == 32
# define BPP 4
# define PIXEL_TYPE uint32_t
#else
@@ -146,7 +152,7 @@ static void glue(draw_line12_, DEPTH)(void *opaque,
static void glue(draw_line16_, DEPTH)(void *opaque,
uint8_t *d, const uint8_t *s, int width, int deststep)
{
-#if defined(HOST_WORDS_BIGENDIAN) == defined(TARGET_WORDS_BIGENDIAN)
+#if DEPTH == 16 && defined(HOST_WORDS_BIGENDIAN) == defined(TARGET_WORDS_BIGENDIAN)
memcpy(d, s, width * 2);
#else
uint16_t v;
diff --git a/hw/display/omap_lcdc.c b/hw/display/omap_lcdc.c
index 07a5effe0..ce1058bf8 100644
--- a/hw/display/omap_lcdc.c
+++ b/hw/display/omap_lcdc.c
@@ -71,9 +71,47 @@ static void omap_lcd_interrupts(struct omap_lcd_panel_s *s)
#define draw_line_func drawfn
+#define DEPTH 8
+#include "omap_lcd_template.h"
+#define DEPTH 15
+#include "omap_lcd_template.h"
+#define DEPTH 16
+#include "omap_lcd_template.h"
#define DEPTH 32
#include "omap_lcd_template.h"
+static draw_line_func draw_line_table2[33] = {
+ [0 ... 32] = NULL,
+ [8] = draw_line2_8,
+ [15] = draw_line2_15,
+ [16] = draw_line2_16,
+ [32] = draw_line2_32,
+}, draw_line_table4[33] = {
+ [0 ... 32] = NULL,
+ [8] = draw_line4_8,
+ [15] = draw_line4_15,
+ [16] = draw_line4_16,
+ [32] = draw_line4_32,
+}, draw_line_table8[33] = {
+ [0 ... 32] = NULL,
+ [8] = draw_line8_8,
+ [15] = draw_line8_15,
+ [16] = draw_line8_16,
+ [32] = draw_line8_32,
+}, draw_line_table12[33] = {
+ [0 ... 32] = NULL,
+ [8] = draw_line12_8,
+ [15] = draw_line12_15,
+ [16] = draw_line12_16,
+ [32] = draw_line12_32,
+}, draw_line_table16[33] = {
+ [0 ... 32] = NULL,
+ [8] = draw_line16_8,
+ [15] = draw_line16_15,
+ [16] = draw_line16_16,
+ [32] = draw_line16_32,
+};
+
static void omap_update_display(void *opaque)
{
struct omap_lcd_panel_s *omap_lcd = (struct omap_lcd_panel_s *) opaque;
@@ -105,25 +143,25 @@ static void omap_update_display(void *opaque)
/* Colour depth */
switch ((omap_lcd->palette[0] >> 12) & 7) {
case 1:
- draw_line = draw_line2_32;
+ draw_line = draw_line_table2[surface_bits_per_pixel(surface)];
bpp = 2;
break;
case 2:
- draw_line = draw_line4_32;
+ draw_line = draw_line_table4[surface_bits_per_pixel(surface)];
bpp = 4;
break;
case 3:
- draw_line = draw_line8_32;
+ draw_line = draw_line_table8[surface_bits_per_pixel(surface)];
bpp = 8;
break;
case 4 ... 7:
if (!omap_lcd->tft)
- draw_line = draw_line12_32;
+ draw_line = draw_line_table12[surface_bits_per_pixel(surface)];
else
- draw_line = draw_line16_32;
+ draw_line = draw_line_table16[surface_bits_per_pixel(surface)];
bpp = 16;
break;
diff --git a/hw/display/pl110.c b/hw/display/pl110.c
index c069c0b7f..d589959f1 100644
--- a/hw/display/pl110.c
+++ b/hw/display/pl110.c
@@ -12,7 +12,6 @@
#include "ui/console.h"
#include "framebuffer.h"
#include "ui/pixel_ops.h"
-#include "qemu/log.h"
#define PL110_CR_EN 0x001
#define PL110_CR_BGR 0x100
diff --git a/hw/display/qxl.c b/hw/display/qxl.c
index 0e2682d28..919dc5cd3 100644
--- a/hw/display/qxl.c
+++ b/hw/display/qxl.c
@@ -504,7 +504,6 @@ static void interface_set_compression_level(QXLInstance *sin, int level)
qxl_rom_set_dirty(qxl);
}
-#if SPICE_NEEDS_SET_MM_TIME
static void interface_set_mm_time(QXLInstance *sin, uint32_t mm_time)
{
PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
@@ -518,7 +517,6 @@ static void interface_set_mm_time(QXLInstance *sin, uint32_t mm_time)
qxl->rom->mm_clock = cpu_to_le32(mm_time);
qxl_rom_set_dirty(qxl);
}
-#endif
static void interface_get_init_info(QXLInstance *sin, QXLDevInitInfo *info)
{
@@ -895,8 +893,7 @@ static void interface_update_area_complete(QXLInstance *sin,
int qxl_i;
qemu_mutex_lock(&qxl->ssd.lock);
- if (surface_id != 0 || !num_updated_rects ||
- !qxl->render_update_cookie_num) {
+ if (surface_id != 0 || !qxl->render_update_cookie_num) {
qemu_mutex_unlock(&qxl->ssd.lock);
return;
}
@@ -1071,9 +1068,7 @@ static const QXLInterface qxl_interface = {
.attache_worker = interface_attach_worker,
.set_compression_level = interface_set_compression_level,
-#if SPICE_NEEDS_SET_MM_TIME
.set_mm_time = interface_set_mm_time,
-#endif
.get_init_info = interface_get_init_info,
/* the callbacks below are called from spice server thread context */
@@ -1248,7 +1243,6 @@ static int qxl_add_memslot(PCIQXLDevice *d, uint32_t slot_id, uint64_t delta,
int pci_region;
pcibus_t pci_start;
pcibus_t pci_end;
- MemoryRegion *mr;
intptr_t virt_start;
QXLDevMemSlot memslot;
int i;
@@ -1295,11 +1289,11 @@ static int qxl_add_memslot(PCIQXLDevice *d, uint32_t slot_id, uint64_t delta,
switch (pci_region) {
case QXL_RAM_RANGE_INDEX:
- mr = &d->vga.vram;
+ virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vga.vram);
break;
case QXL_VRAM_RANGE_INDEX:
case 4 /* vram 64bit */:
- mr = &d->vram_bar;
+ virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vram_bar);
break;
default:
/* should not happen */
@@ -1307,7 +1301,6 @@ static int qxl_add_memslot(PCIQXLDevice *d, uint32_t slot_id, uint64_t delta,
return 1;
}
- virt_start = (intptr_t)memory_region_get_ram_ptr(mr);
memslot.slot_id = slot_id;
memslot.slot_group_id = MEMSLOT_GROUP_GUEST; /* guest group */
memslot.virt_start = virt_start + (guest_start - pci_start);
@@ -1317,8 +1310,7 @@ static int qxl_add_memslot(PCIQXLDevice *d, uint32_t slot_id, uint64_t delta,
qxl_rom_set_dirty(d);
qemu_spice_add_memslot(&d->ssd, &memslot, async);
- d->guest_slots[slot_id].mr = mr;
- d->guest_slots[slot_id].offset = memslot.virt_start - virt_start;
+ d->guest_slots[slot_id].ptr = (void*)memslot.virt_start;
d->guest_slots[slot_id].size = memslot.virt_end - memslot.virt_start;
d->guest_slots[slot_id].delta = delta;
d->guest_slots[slot_id].active = 1;
@@ -1345,60 +1337,39 @@ static void qxl_reset_surfaces(PCIQXLDevice *d)
}
/* can be also called from spice server thread context */
-static bool qxl_get_check_slot_offset(PCIQXLDevice *qxl, QXLPHYSICAL pqxl,
- uint32_t *s, uint64_t *o)
+void *qxl_phys2virt(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, int group_id)
{
uint64_t phys = le64_to_cpu(pqxl);
uint32_t slot = (phys >> (64 - 8)) & 0xff;
uint64_t offset = phys & 0xffffffffffff;
- if (slot >= NUM_MEMSLOTS) {
- qxl_set_guest_bug(qxl, "slot too large %d >= %d", slot,
- NUM_MEMSLOTS);
- return false;
- }
- if (!qxl->guest_slots[slot].active) {
- qxl_set_guest_bug(qxl, "inactive slot %d\n", slot);
- return false;
- }
- if (offset < qxl->guest_slots[slot].delta) {
- qxl_set_guest_bug(qxl,
- "slot %d offset %"PRIu64" < delta %"PRIu64"\n",
- slot, offset, qxl->guest_slots[slot].delta);
- return false;
- }
- offset -= qxl->guest_slots[slot].delta;
- if (offset > qxl->guest_slots[slot].size) {
- qxl_set_guest_bug(qxl,
- "slot %d offset %"PRIu64" > size %"PRIu64"\n",
- slot, offset, qxl->guest_slots[slot].size);
- return false;
- }
-
- *s = slot;
- *o = offset;
- return true;
-}
-
-/* can be also called from spice server thread context */
-void *qxl_phys2virt(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, int group_id)
-{
- uint64_t offset;
- uint32_t slot;
- void *ptr;
-
switch (group_id) {
case MEMSLOT_GROUP_HOST:
- offset = le64_to_cpu(pqxl) & 0xffffffffffff;
return (void *)(intptr_t)offset;
case MEMSLOT_GROUP_GUEST:
- if (!qxl_get_check_slot_offset(qxl, pqxl, &slot, &offset)) {
+ if (slot >= NUM_MEMSLOTS) {
+ qxl_set_guest_bug(qxl, "slot too large %d >= %d", slot,
+ NUM_MEMSLOTS);
+ return NULL;
+ }
+ if (!qxl->guest_slots[slot].active) {
+ qxl_set_guest_bug(qxl, "inactive slot %d\n", slot);
return NULL;
}
- ptr = memory_region_get_ram_ptr(qxl->guest_slots[slot].mr);
- ptr += qxl->guest_slots[slot].offset;
- ptr += offset;
- return ptr;
+ if (offset < qxl->guest_slots[slot].delta) {
+ qxl_set_guest_bug(qxl,
+ "slot %d offset %"PRIu64" < delta %"PRIu64"\n",
+ slot, offset, qxl->guest_slots[slot].delta);
+ return NULL;
+ }
+ offset -= qxl->guest_slots[slot].delta;
+ if (offset > qxl->guest_slots[slot].size) {
+ qxl_set_guest_bug(qxl,
+ "slot %d offset %"PRIu64" > size %"PRIu64"\n",
+ slot, offset, qxl->guest_slots[slot].size);
+ return NULL;
+ }
+ return qxl->guest_slots[slot].ptr + offset;
}
return NULL;
}
@@ -1813,24 +1784,9 @@ static void qxl_hw_update(void *opaque)
qxl_render_update(qxl);
}
-static void qxl_dirty_one_surface(PCIQXLDevice *qxl, QXLPHYSICAL pqxl,
- uint32_t height, int32_t stride)
-{
- uint64_t offset, size;
- uint32_t slot;
- bool rc;
-
- rc = qxl_get_check_slot_offset(qxl, pqxl, &slot, &offset);
- assert(rc == true);
- size = (uint64_t)height * abs(stride);
- trace_qxl_surfaces_dirty(qxl->id, offset, size);
- qxl_set_dirty(qxl->guest_slots[slot].mr,
- qxl->guest_slots[slot].offset + offset,
- qxl->guest_slots[slot].offset + offset + size);
-}
-
static void qxl_dirty_surfaces(PCIQXLDevice *qxl)
{
+ uintptr_t vram_start;
int i;
if (qxl->mode != QXL_MODE_NATIVE && qxl->mode != QXL_MODE_COMPAT) {
@@ -1838,13 +1794,16 @@ static void qxl_dirty_surfaces(PCIQXLDevice *qxl)
}
/* dirty the primary surface */
- qxl_dirty_one_surface(qxl, qxl->guest_primary.surface.mem,
- qxl->guest_primary.surface.height,
- qxl->guest_primary.surface.stride);
+ qxl_set_dirty(&qxl->vga.vram, qxl->shadow_rom.draw_area_offset,
+ qxl->shadow_rom.surface0_area_size);
+
+ vram_start = (uintptr_t)memory_region_get_ram_ptr(&qxl->vram_bar);
/* dirty the off-screen surfaces */
for (i = 0; i < qxl->ssd.num_surfaces; i++) {
QXLSurfaceCmd *cmd;
+ intptr_t surface_offset;
+ int surface_size;
if (qxl->guest_surfaces.cmds[i] == 0) {
continue;
@@ -1854,9 +1813,15 @@ static void qxl_dirty_surfaces(PCIQXLDevice *qxl)
MEMSLOT_GROUP_GUEST);
assert(cmd);
assert(cmd->type == QXL_SURFACE_CMD_CREATE);
- qxl_dirty_one_surface(qxl, cmd->u.surface_create.data,
- cmd->u.surface_create.height,
- cmd->u.surface_create.stride);
+ surface_offset = (intptr_t)qxl_phys2virt(qxl,
+ cmd->u.surface_create.data,
+ MEMSLOT_GROUP_GUEST);
+ assert(surface_offset);
+ surface_offset -= vram_start;
+ surface_size = cmd->u.surface_create.height *
+ abs(cmd->u.surface_create.stride);
+ trace_qxl_surfaces_dirty(qxl->id, i, (int)surface_offset, surface_size);
+ qxl_set_dirty(&qxl->vram_bar, surface_offset, surface_size);
}
}
@@ -1949,7 +1914,7 @@ static void qxl_init_ramsize(PCIQXLDevice *qxl)
/* vram (surfaces, 64bit, bar 4+5) */
if (qxl->vram_size_mb != -1) {
- qxl->vram_size = (uint64_t)qxl->vram_size_mb * 1024 * 1024;
+ qxl->vram_size = qxl->vram_size_mb * 1024 * 1024;
}
if (qxl->vram_size < qxl->vram32_size) {
qxl->vram_size = qxl->vram32_size;
@@ -2055,9 +2020,9 @@ static void qxl_realize_common(PCIQXLDevice *qxl, Error **errp)
dprint(qxl, 1, "ram/%s: %d MB [region 0]\n",
qxl->id == 0 ? "pri" : "sec",
qxl->vga.vram_size / (1024*1024));
- dprint(qxl, 1, "vram/32: %" PRIx64 "d MB [region 1]\n",
+ dprint(qxl, 1, "vram/32: %d MB [region 1]\n",
qxl->vram32_size / (1024*1024));
- dprint(qxl, 1, "vram/64: %" PRIx64 "d MB %s\n",
+ dprint(qxl, 1, "vram/64: %d MB %s\n",
qxl->vram_size / (1024*1024),
qxl->vram32_size < qxl->vram_size ? "[region 4]" : "[unmapped]");
@@ -2311,7 +2276,7 @@ static VMStateDescription qxl_vmstate = {
static Property qxl_properties[] = {
DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size,
64 * 1024 * 1024),
- DEFINE_PROP_UINT64("vram_size", PCIQXLDevice, vram32_size,
+ DEFINE_PROP_UINT32("vram_size", PCIQXLDevice, vram32_size,
64 * 1024 * 1024),
DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision,
QXL_DEFAULT_REVISION),
diff --git a/hw/display/qxl.h b/hw/display/qxl.h
index d2d49dd93..2ddf065e1 100644
--- a/hw/display/qxl.h
+++ b/hw/display/qxl.h
@@ -1,5 +1,5 @@
#ifndef HW_QXL_H
-#define HW_QXL_H
+#define HW_QXL_H 1
#include "qemu-common.h"
@@ -53,8 +53,7 @@ typedef struct PCIQXLDevice {
struct guest_slots {
QXLMemSlot slot;
- MemoryRegion *mr;
- uint64_t offset;
+ void *ptr;
uint64_t size;
uint64_t delta;
uint32_t active;
@@ -105,9 +104,9 @@ typedef struct PCIQXLDevice {
#endif
/* vram pci bar */
- uint64_t vram_size;
+ uint32_t vram_size;
MemoryRegion vram_bar;
- uint64_t vram32_size;
+ uint32_t vram32_size;
MemoryRegion vram32_bar;
/* io bar */
diff --git a/hw/display/ssd0323.c b/hw/display/ssd0323.c
index 6d1faf44a..14c1bf339 100644
--- a/hw/display/ssd0323.c
+++ b/hw/display/ssd0323.c
@@ -361,7 +361,7 @@ static const GraphicHwOps ssd0323_ops = {
.gfx_update = ssd0323_update_display,
};
-static void ssd0323_realize(SSISlave *d, Error **errp)
+static int ssd0323_init(SSISlave *d)
{
DeviceState *dev = DEVICE(d);
ssd0323_state *s = FROM_SSI_SLAVE(ssd0323_state, d);
@@ -375,13 +375,14 @@ static void ssd0323_realize(SSISlave *d, Error **errp)
register_savevm(dev, "ssd0323_oled", -1, 1,
ssd0323_save, ssd0323_load, s);
+ return 0;
}
static void ssd0323_class_init(ObjectClass *klass, void *data)
{
SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
- k->realize = ssd0323_realize;
+ k->init = ssd0323_init;
k->transfer = ssd0323_transfer;
k->cs_polarity = SSI_CS_HIGH;
}
diff --git a/hw/display/tc6393xb.c b/hw/display/tc6393xb.c
index 92f7120ac..da3ceceb0 100644
--- a/hw/display/tc6393xb.c
+++ b/hw/display/tc6393xb.c
@@ -12,7 +12,6 @@
*/
#include "qemu/osdep.h"
#include "qapi/error.h"
-#include "qemu/host-utils.h"
#include "hw/hw.h"
#include "hw/devices.h"
#include "hw/block/flash.h"
diff --git a/hw/display/trace-events b/hw/display/trace-events
deleted file mode 100644
index 332ababd8..000000000
--- a/hw/display/trace-events
+++ /dev/null
@@ -1,122 +0,0 @@
-# See docs/tracing.txt for syntax documentation.
-
-# hw/display/jazz_led.c
-jazz_led_read(uint64_t addr, uint8_t val) "read addr=0x%"PRIx64": 0x%x"
-jazz_led_write(uint64_t addr, uint8_t new) "write addr=0x%"PRIx64": 0x%x"
-
-# hw/display/xenfb.c
-xenfb_mouse_event(void *opaque, int dx, int dy, int dz, int button_state, int abs_pointer_wanted) "%p x %d y %d z %d bs %#x abs %d"
-xenfb_input_connected(void *xendev, int abs_pointer_wanted) "%p abs %d"
-
-# hw/display/g364fb.c
-g364fb_read(uint64_t addr, uint32_t val) "read addr=0x%"PRIx64": 0x%x"
-g364fb_write(uint64_t addr, uint32_t new) "write addr=0x%"PRIx64": 0x%x"
-
-# hw/display/milkymist-tmu2.c
-milkymist_tmu2_memory_read(uint32_t addr, uint32_t value) "addr %08x value %08x"
-milkymist_tmu2_memory_write(uint32_t addr, uint32_t value) "addr %08x value %08x"
-milkymist_tmu2_start(void) "Start TMU"
-milkymist_tmu2_pulse_irq(void) "Pulse IRQ"
-
-# hw/display/milkymist-vgafb.c
-milkymist_vgafb_memory_read(uint32_t addr, uint32_t value) "addr %08x value %08x"
-milkymist_vgafb_memory_write(uint32_t addr, uint32_t value) "addr %08x value %08x"
-
-# hw/display/vmware_vga.c
-vmware_value_read(uint32_t index, uint32_t value) "index %d, value 0x%x"
-vmware_value_write(uint32_t index, uint32_t value) "index %d, value 0x%x"
-vmware_palette_read(uint32_t index, uint32_t value) "index %d, value 0x%x"
-vmware_palette_write(uint32_t index, uint32_t value) "index %d, value 0x%x"
-vmware_scratch_read(uint32_t index, uint32_t value) "index %d, value 0x%x"
-vmware_scratch_write(uint32_t index, uint32_t value) "index %d, value 0x%x"
-vmware_setmode(uint32_t w, uint32_t h, uint32_t bpp) "%dx%d @ %d bpp"
-
-# hw/display/virtio-gpu.c
-virtio_gpu_features(bool virgl) "virgl %d"
-virtio_gpu_cmd_get_display_info(void) ""
-virtio_gpu_cmd_get_caps(void) ""
-virtio_gpu_cmd_set_scanout(uint32_t id, uint32_t res, uint32_t w, uint32_t h, uint32_t x, uint32_t y) "id %d, res 0x%x, w %d, h %d, x %d, y %d"
-virtio_gpu_cmd_res_create_2d(uint32_t res, uint32_t fmt, uint32_t w, uint32_t h) "res 0x%x, fmt 0x%x, w %d, h %d"
-virtio_gpu_cmd_res_create_3d(uint32_t res, uint32_t fmt, uint32_t w, uint32_t h, uint32_t d) "res 0x%x, fmt 0x%x, w %d, h %d, d %d"
-virtio_gpu_cmd_res_unref(uint32_t res) "res 0x%x"
-virtio_gpu_cmd_res_back_attach(uint32_t res) "res 0x%x"
-virtio_gpu_cmd_res_back_detach(uint32_t res) "res 0x%x"
-virtio_gpu_cmd_res_xfer_toh_2d(uint32_t res) "res 0x%x"
-virtio_gpu_cmd_res_xfer_toh_3d(uint32_t res) "res 0x%x"
-virtio_gpu_cmd_res_xfer_fromh_3d(uint32_t res) "res 0x%x"
-virtio_gpu_cmd_res_flush(uint32_t res, uint32_t w, uint32_t h, uint32_t x, uint32_t y) "res 0x%x, w %d, h %d, x %d, y %d"
-virtio_gpu_cmd_ctx_create(uint32_t ctx, const char *name) "ctx 0x%x, name %s"
-virtio_gpu_cmd_ctx_destroy(uint32_t ctx) "ctx 0x%x"
-virtio_gpu_cmd_ctx_res_attach(uint32_t ctx, uint32_t res) "ctx 0x%x, res 0x%x"
-virtio_gpu_cmd_ctx_res_detach(uint32_t ctx, uint32_t res) "ctx 0x%x, res 0x%x"
-virtio_gpu_cmd_ctx_submit(uint32_t ctx, uint32_t size) "ctx 0x%x, size %d"
-virtio_gpu_update_cursor(uint32_t scanout, uint32_t x, uint32_t y, const char *type, uint32_t res) "scanout %d, x %d, y %d, %s, res 0x%x"
-virtio_gpu_fence_ctrl(uint64_t fence, uint32_t type) "fence 0x%" PRIx64 ", type 0x%x"
-virtio_gpu_fence_resp(uint64_t fence) "fence 0x%" PRIx64
-
-# hw/display/qxl.c
-disable qxl_interface_set_mm_time(int qid, uint32_t mm_time) "%d %d"
-disable qxl_io_write_vga(int qid, const char *mode, uint32_t addr, uint32_t val) "%d %s addr=%u val=%u"
-qxl_create_guest_primary(int qid, uint32_t width, uint32_t height, uint64_t mem, uint32_t format, uint32_t position) "%d %ux%u mem=%" PRIx64 " %u,%u"
-qxl_create_guest_primary_rest(int qid, int32_t stride, uint32_t type, uint32_t flags) "%d %d,%d,%d"
-qxl_destroy_primary(int qid) "%d"
-qxl_enter_vga_mode(int qid) "%d"
-qxl_exit_vga_mode(int qid) "%d"
-qxl_hard_reset(int qid, int64_t loadvm) "%d loadvm=%"PRId64
-qxl_interface_async_complete_io(int qid, uint32_t current_async, void *cookie) "%d current=%d cookie=%p"
-qxl_interface_attach_worker(int qid) "%d"
-qxl_interface_get_init_info(int qid) "%d"
-qxl_interface_set_compression_level(int qid, int64_t level) "%d %"PRId64
-qxl_interface_update_area_complete(int qid, uint32_t surface_id, uint32_t dirty_left, uint32_t dirty_right, uint32_t dirty_top, uint32_t dirty_bottom) "%d surface=%d [%d,%d,%d,%d]"
-qxl_interface_update_area_complete_rest(int qid, uint32_t num_updated_rects) "%d #=%d"
-qxl_interface_update_area_complete_overflow(int qid, int max) "%d max=%d"
-qxl_interface_update_area_complete_schedule_bh(int qid, uint32_t num_dirty) "%d #dirty=%d"
-qxl_io_destroy_primary_ignored(int qid, const char *mode) "%d %s"
-qxl_io_log(int qid, const uint8_t *log_buf) "%d %s"
-qxl_io_read_unexpected(int qid) "%d"
-qxl_io_unexpected_vga_mode(int qid, uint64_t addr, uint64_t val, const char *desc) "%d 0x%"PRIx64"=%"PRIu64" (%s)"
-qxl_io_write(int qid, const char *mode, uint64_t addr, const char *aname, uint64_t val, unsigned size, int async) "%d %s addr=%"PRIu64 " (%s) val=%"PRIu64" size=%u async=%d"
-qxl_memslot_add_guest(int qid, uint32_t slot_id, uint64_t guest_start, uint64_t guest_end) "%d %u: guest phys 0x%"PRIx64 " - 0x%" PRIx64
-qxl_post_load(int qid, const char *mode) "%d %s"
-qxl_pre_load(int qid) "%d"
-qxl_pre_save(int qid) "%d"
-qxl_reset_surfaces(int qid) "%d"
-qxl_ring_command_check(int qid, const char *mode) "%d %s"
-qxl_ring_command_get(int qid, const char *mode) "%d %s"
-qxl_ring_command_req_notification(int qid) "%d"
-qxl_ring_cursor_check(int qid, const char *mode) "%d %s"
-qxl_ring_cursor_get(int qid, const char *mode) "%d %s"
-qxl_ring_cursor_req_notification(int qid) "%d"
-qxl_ring_res_push(int qid, const char *mode, uint32_t surface_count, uint32_t free_res, void *last_release, const char *notify) "%d %s s#=%d res#=%d last=%p notify=%s"
-qxl_ring_res_push_rest(int qid, uint32_t ring_has, uint32_t ring_size, uint32_t prod, uint32_t cons) "%d ring %d/%d [%d,%d]"
-qxl_ring_res_put(int qid, uint32_t free_res) "%d #res=%d"
-qxl_set_mode(int qid, int modenr, uint32_t x_res, uint32_t y_res, uint32_t bits, uint64_t devmem) "%d mode=%d [ x=%d y=%d @ bpp=%d devmem=0x%" PRIx64 " ]"
-qxl_soft_reset(int qid) "%d"
-qxl_spice_destroy_surfaces_complete(int qid) "%d"
-qxl_spice_destroy_surfaces(int qid, int async) "%d async=%d"
-qxl_spice_destroy_surface_wait_complete(int qid, uint32_t id) "%d sid=%d"
-qxl_spice_destroy_surface_wait(int qid, uint32_t id, int async) "%d sid=%d async=%d"
-qxl_spice_flush_surfaces_async(int qid, uint32_t surface_count, uint32_t num_free_res) "%d s#=%d, res#=%d"
-qxl_spice_monitors_config(int qid) "%d"
-qxl_spice_loadvm_commands(int qid, void *ext, uint32_t count) "%d ext=%p count=%d"
-qxl_spice_oom(int qid) "%d"
-qxl_spice_reset_cursor(int qid) "%d"
-qxl_spice_reset_image_cache(int qid) "%d"
-qxl_spice_reset_memslots(int qid) "%d"
-qxl_spice_update_area(int qid, uint32_t surface_id, uint32_t left, uint32_t right, uint32_t top, uint32_t bottom) "%d sid=%d [%d,%d,%d,%d]"
-qxl_spice_update_area_rest(int qid, uint32_t num_dirty_rects, uint32_t clear_dirty_region) "%d #d=%d clear=%d"
-qxl_surfaces_dirty(int qid, uint64_t offset, uint64_t size) "%d offset=0x%"PRIx64" size=0x%"PRIx64
-qxl_send_events(int qid, uint32_t events) "%d %d"
-qxl_send_events_vm_stopped(int qid, uint32_t events) "%d %d"
-qxl_set_guest_bug(int qid) "%d"
-qxl_interrupt_client_monitors_config(int qid, int num_heads, void *heads) "%d %d %p"
-qxl_client_monitors_config_unsupported_by_guest(int qid, uint32_t int_mask, void *client_monitors_config) "%d %X %p"
-qxl_client_monitors_config_unsupported_by_device(int qid, int revision) "%d revision=%d"
-qxl_client_monitors_config_capped(int qid, int requested, int limit) "%d %d %d"
-qxl_client_monitors_config_crc(int qid, unsigned size, uint32_t crc32) "%d %u %u"
-qxl_set_client_capabilities_unsupported_by_revision(int qid, int revision) "%d revision=%d"
-
-# hw/display/qxl-render.c
-qxl_render_blit(int32_t stride, int32_t left, int32_t right, int32_t top, int32_t bottom) "stride=%d [%d, %d, %d, %d]"
-qxl_render_guest_primary_resized(int32_t width, int32_t height, int32_t stride, int32_t bytes_pp, int32_t bits_pp) "%dx%d, stride %d, bpp %d, depth %d"
-qxl_render_update_area_done(void *cookie) "%p"
diff --git a/hw/display/vga.c b/hw/display/vga.c
index 2a88b3c1b..9ebc54f22 100644
--- a/hw/display/vga.c
+++ b/hw/display/vga.c
@@ -700,7 +700,9 @@ static void vbe_update_vgaregs(VGACommonState *s)
static uint32_t vbe_ioport_read_index(void *opaque, uint32_t addr)
{
VGACommonState *s = opaque;
- return s->vbe_index;
+ uint32_t val;
+ val = s->vbe_index;
+ return val;
}
uint32_t vbe_ioport_read_data(void *opaque, uint32_t addr)
diff --git a/hw/display/vga.h b/hw/display/vga.h
index 16886f5ee..d917046da 100644
--- a/hw/display/vga.h
+++ b/hw/display/vga.h
@@ -14,8 +14,8 @@
*
*/
-#ifndef LINUX_VIDEO_VGA_H
-#define LINUX_VIDEO_VGA_H
+#ifndef __linux_video_vga_h__
+#define __linux_video_vga_h__
/* Some of the code below is taken from SVGAlib. The original,
unmodified copyright notice for that code is below. */
@@ -156,4 +156,4 @@
/* VGA graphics controller bit masks */
#define VGA_GR06_GRAPHICS_MODE 0x01
-#endif /* LINUX_VIDEO_VGA_H */
+#endif /* __linux_video_vga_h__ */
diff --git a/hw/display/vga_int.h b/hw/display/vga_int.h
index dd6c958da..3ce5544ef 100644
--- a/hw/display/vga_int.h
+++ b/hw/display/vga_int.h
@@ -21,11 +21,10 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-
#ifndef HW_VGA_INT_H
-#define HW_VGA_INT_H
+#define HW_VGA_INT_H 1
-#include "hw/hw.h"
+#include <hw/hw.h>
#include "exec/memory.h"
#define ST01_V_RETRACE 0x08
diff --git a/hw/display/virtio-gpu-3d.c b/hw/display/virtio-gpu-3d.c
index 758d33a09..fa192946a 100644
--- a/hw/display/virtio-gpu-3d.c
+++ b/hw/display/virtio-gpu-3d.c
@@ -17,11 +17,10 @@
#include "trace.h"
#include "hw/virtio/virtio.h"
#include "hw/virtio/virtio-gpu.h"
-#include "qapi/error.h"
#ifdef CONFIG_VIRGL
-#include <virglrenderer.h>
+#include "virglrenderer.h"
static struct virgl_renderer_callbacks virtio_gpu_3d_cbs;
@@ -128,7 +127,7 @@ static void virgl_cmd_resource_flush(VirtIOGPU *g,
trace_virtio_gpu_cmd_res_flush(rf.resource_id,
rf.r.width, rf.r.height, rf.r.x, rf.r.y);
- for (i = 0; i < g->conf.max_outputs; i++) {
+ for (i = 0; i < VIRTIO_GPU_MAX_SCANOUT; i++) {
if (g->scanout[i].resource_id != rf.resource_id) {
continue;
}
@@ -147,7 +146,7 @@ static void virgl_cmd_set_scanout(VirtIOGPU *g,
trace_virtio_gpu_cmd_set_scanout(ss.scanout_id, ss.resource_id,
ss.r.width, ss.r.height, ss.r.x, ss.r.y);
- if (ss.scanout_id >= g->conf.max_outputs) {
+ if (ss.scanout_id >= VIRTIO_GPU_MAX_SCANOUT) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: illegal scanout id specified %d",
__func__, ss.scanout_id);
cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_SCANOUT_ID;
@@ -171,14 +170,13 @@ static void virgl_cmd_set_scanout(VirtIOGPU *g,
virgl_renderer_force_ctx_0();
dpy_gl_scanout(g->scanout[ss.scanout_id].con, info.tex_id,
info.flags & 1 /* FIXME: Y_0_TOP */,
- info.width, info.height,
ss.r.x, ss.r.y, ss.r.width, ss.r.height);
} else {
if (ss.scanout_id != 0) {
dpy_gfx_replace_surface(g->scanout[ss.scanout_id].con, NULL);
}
dpy_gl_scanout(g->scanout[ss.scanout_id].con, 0, false,
- 0, 0, 0, 0, 0, 0);
+ 0, 0, 0, 0);
}
g->scanout[ss.scanout_id].resource_id = ss.resource_id;
}
@@ -285,7 +283,7 @@ static void virgl_resource_attach_backing(VirtIOGPU *g,
VIRTIO_GPU_FILL_CMD(att_rb);
trace_virtio_gpu_cmd_res_back_attach(att_rb.resource_id);
- ret = virtio_gpu_create_mapping_iov(&att_rb, cmd, NULL, &res_iovs);
+ ret = virtio_gpu_create_mapping_iov(&att_rb, cmd, &res_iovs);
if (ret != 0) {
cmd->error = VIRTIO_GPU_RESP_ERR_UNSPEC;
return;
@@ -581,7 +579,7 @@ void virtio_gpu_virgl_reset(VirtIOGPU *g)
if (i != 0) {
dpy_gfx_replace_surface(g->scanout[i].con, NULL);
}
- dpy_gl_scanout(g->scanout[i].con, 0, false, 0, 0, 0, 0, 0, 0);
+ dpy_gl_scanout(g->scanout[i].con, 0, false, 0, 0, 0, 0);
}
}
diff --git a/hw/display/virtio-gpu-pci.c b/hw/display/virtio-gpu-pci.c
index 34a724c75..a71b230d3 100644
--- a/hw/display/virtio-gpu-pci.c
+++ b/hw/display/virtio-gpu-pci.c
@@ -30,7 +30,9 @@ static void virtio_gpu_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp)
int i;
qdev_set_parent_bus(vdev, BUS(&vpci_dev->bus));
- virtio_pci_force_virtio_1(vpci_dev);
+ /* force virtio-1.0 */
+ vpci_dev->flags &= ~VIRTIO_PCI_FLAG_DISABLE_MODERN;
+ vpci_dev->flags |= VIRTIO_PCI_FLAG_DISABLE_LEGACY;
object_property_set_bool(OBJECT(vdev), true, "realized", errp);
for (i = 0; i < g->conf.max_outputs; i++) {
diff --git a/hw/display/virtio-gpu.c b/hw/display/virtio-gpu.c
index 7fe6ed8bf..c181fb364 100644
--- a/hw/display/virtio-gpu.c
+++ b/hw/display/virtio-gpu.c
@@ -19,17 +19,12 @@
#include "hw/virtio/virtio.h"
#include "hw/virtio/virtio-gpu.h"
#include "hw/virtio/virtio-bus.h"
-#include "migration/migration.h"
-#include "qemu/log.h"
-#include "qapi/error.h"
-
-#define VIRTIO_GPU_VM_VERSION 1
static struct virtio_gpu_simple_resource*
virtio_gpu_find_resource(VirtIOGPU *g, uint32_t resource_id);
#ifdef CONFIG_VIRGL
-#include <virglrenderer.h>
+#include "virglrenderer.h"
#define VIRGL(_g, _virgl, _simple, ...) \
do { \
if (_g->use_virgl_renderer) { \
@@ -97,7 +92,7 @@ static void update_cursor_data_virgl(VirtIOGPU *g,
static void update_cursor(VirtIOGPU *g, struct virtio_gpu_update_cursor *cursor)
{
struct virtio_gpu_scanout *s;
- bool move = cursor->hdr.type == VIRTIO_GPU_CMD_MOVE_CURSOR;
+ bool move = cursor->hdr.type != VIRTIO_GPU_CMD_MOVE_CURSOR;
if (cursor->pos.scanout_id >= g->conf.max_outputs) {
return;
@@ -110,7 +105,7 @@ static void update_cursor(VirtIOGPU *g, struct virtio_gpu_update_cursor *cursor)
move ? "move" : "update",
cursor->resource_id);
- if (!move) {
+ if (move) {
if (!s->current_cursor) {
s->current_cursor = cursor_alloc(64, 64);
}
@@ -123,11 +118,6 @@ static void update_cursor(VirtIOGPU *g, struct virtio_gpu_update_cursor *cursor)
g, s, cursor->resource_id);
}
dpy_cursor_define(s->con, s->current_cursor);
-
- s->cursor = *cursor;
- } else {
- s->cursor.pos.x = cursor->pos.x;
- s->cursor.pos.y = cursor->pos.y;
}
dpy_mouse_set(s->con, cursor->pos.x, cursor->pos.y,
cursor->resource_id ? 1 : 0);
@@ -474,7 +464,7 @@ static void virtio_gpu_resource_flush(VirtIOGPU *g,
pixman_region_init_rect(&flush_region,
rf.r.x, rf.r.y, rf.r.width, rf.r.height);
- for (i = 0; i < g->conf.max_outputs; i++) {
+ for (i = 0; i < VIRTIO_GPU_MAX_SCANOUT; i++) {
struct virtio_gpu_scanout *scanout;
pixman_region16_t region, finalregion;
pixman_box16_t *extents;
@@ -503,11 +493,6 @@ static void virtio_gpu_resource_flush(VirtIOGPU *g,
pixman_region_fini(&flush_region);
}
-static void virtio_unref_resource(pixman_image_t *image, void *data)
-{
- pixman_image_unref(data);
-}
-
static void virtio_gpu_set_scanout(VirtIOGPU *g,
struct virtio_gpu_ctrl_command *cmd)
{
@@ -522,13 +507,6 @@ static void virtio_gpu_set_scanout(VirtIOGPU *g,
trace_virtio_gpu_cmd_set_scanout(ss.scanout_id, ss.resource_id,
ss.r.width, ss.r.height, ss.r.x, ss.r.y);
- if (ss.scanout_id >= g->conf.max_outputs) {
- qemu_log_mask(LOG_GUEST_ERROR, "%s: illegal scanout id specified %d",
- __func__, ss.scanout_id);
- cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_SCANOUT_ID;
- return;
- }
-
g->enable = 1;
if (ss.resource_id == 0) {
scanout = &g->scanout[ss.scanout_id];
@@ -538,7 +516,8 @@ static void virtio_gpu_set_scanout(VirtIOGPU *g,
res->scanout_bitmask &= ~(1 << ss.scanout_id);
}
}
- if (ss.scanout_id == 0) {
+ if (ss.scanout_id == 0 ||
+ ss.scanout_id >= g->conf.max_outputs) {
qemu_log_mask(LOG_GUEST_ERROR,
"%s: illegal scanout id specified %d",
__func__, ss.scanout_id);
@@ -553,6 +532,14 @@ static void virtio_gpu_set_scanout(VirtIOGPU *g,
}
/* create a surface for this scanout */
+ if (ss.scanout_id >= VIRTIO_GPU_MAX_SCANOUT ||
+ ss.scanout_id >= g->conf.max_outputs) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: illegal scanout id specified %d",
+ __func__, ss.scanout_id);
+ cmd->error = VIRTIO_GPU_RESP_ERR_INVALID_SCANOUT_ID;
+ return;
+ }
+
res = virtio_gpu_find_resource(g, ss.resource_id);
if (!res) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: illegal resource specified %d\n",
@@ -584,15 +571,8 @@ static void virtio_gpu_set_scanout(VirtIOGPU *g,
!= ((uint8_t *)pixman_image_get_data(res->image) + offset) ||
scanout->width != ss.r.width ||
scanout->height != ss.r.height) {
- pixman_image_t *rect;
- void *ptr = (uint8_t *)pixman_image_get_data(res->image) + offset;
- rect = pixman_image_create_bits(format, ss.r.width, ss.r.height, ptr,
- pixman_image_get_stride(res->image));
- pixman_image_ref(res->image);
- pixman_image_set_destroy_function(rect, virtio_unref_resource,
- res->image);
/* realloc the surface ptr */
- scanout->ds = qemu_create_displaysurface_pixman(rect);
+ scanout->ds = qemu_create_displaysurface_pixman(res->image);
if (!scanout->ds) {
cmd->error = VIRTIO_GPU_RESP_ERR_UNSPEC;
return;
@@ -610,7 +590,7 @@ static void virtio_gpu_set_scanout(VirtIOGPU *g,
int virtio_gpu_create_mapping_iov(struct virtio_gpu_resource_attach_backing *ab,
struct virtio_gpu_ctrl_command *cmd,
- uint64_t **addr, struct iovec **iov)
+ struct iovec **iov)
{
struct virtio_gpu_mem_entry *ents;
size_t esize, s;
@@ -636,16 +616,10 @@ int virtio_gpu_create_mapping_iov(struct virtio_gpu_resource_attach_backing *ab,
}
*iov = g_malloc0(sizeof(struct iovec) * ab->nr_entries);
- if (addr) {
- *addr = g_malloc0(sizeof(uint64_t) * ab->nr_entries);
- }
for (i = 0; i < ab->nr_entries; i++) {
hwaddr len = ents[i].length;
(*iov)[i].iov_len = ents[i].length;
(*iov)[i].iov_base = cpu_physical_memory_map(ents[i].addr, &len, 1);
- if (addr) {
- (*addr)[i] = ents[i].addr;
- }
if (!(*iov)[i].iov_base || len != ents[i].length) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: failed to map MMIO memory for"
" resource %d element %d\n",
@@ -653,10 +627,6 @@ int virtio_gpu_create_mapping_iov(struct virtio_gpu_resource_attach_backing *ab,
virtio_gpu_cleanup_mapping_iov(*iov, i);
g_free(ents);
*iov = NULL;
- if (addr) {
- g_free(*addr);
- *addr = NULL;
- }
return -1;
}
}
@@ -680,8 +650,6 @@ static void virtio_gpu_cleanup_mapping(struct virtio_gpu_simple_resource *res)
virtio_gpu_cleanup_mapping_iov(res->iov, res->iov_cnt);
res->iov = NULL;
res->iov_cnt = 0;
- g_free(res->addrs);
- res->addrs = NULL;
}
static void
@@ -703,7 +671,7 @@ virtio_gpu_resource_attach_backing(VirtIOGPU *g,
return;
}
- ret = virtio_gpu_create_mapping_iov(&ab, cmd, &res->addrs, &res->iov);
+ ret = virtio_gpu_create_mapping_iov(&ab, cmd, &res->iov);
if (ret != 0) {
cmd->error = VIRTIO_GPU_RESP_ERR_UNSPEC;
return;
@@ -911,7 +879,7 @@ static int virtio_gpu_ui_info(void *opaque, uint32_t idx, QemuUIInfo *info)
{
VirtIOGPU *g = opaque;
- if (idx >= g->conf.max_outputs) {
+ if (idx > g->conf.max_outputs) {
return -1;
}
@@ -935,14 +903,8 @@ static void virtio_gpu_gl_block(void *opaque, bool block)
{
VirtIOGPU *g = opaque;
- if (block) {
- g->renderer_blocked++;
- } else {
- g->renderer_blocked--;
- }
- assert(g->renderer_blocked >= 0);
-
- if (g->renderer_blocked == 0) {
+ g->renderer_blocked = block;
+ if (!block) {
virtio_gpu_process_cmdq(g);
}
}
@@ -955,154 +917,11 @@ const GraphicHwOps virtio_gpu_ops = {
.gl_block = virtio_gpu_gl_block,
};
-static const VMStateDescription vmstate_virtio_gpu_scanout = {
- .name = "virtio-gpu-one-scanout",
- .version_id = 1,
- .fields = (VMStateField[]) {
- VMSTATE_UINT32(resource_id, struct virtio_gpu_scanout),
- VMSTATE_UINT32(width, struct virtio_gpu_scanout),
- VMSTATE_UINT32(height, struct virtio_gpu_scanout),
- VMSTATE_INT32(x, struct virtio_gpu_scanout),
- VMSTATE_INT32(y, struct virtio_gpu_scanout),
- VMSTATE_UINT32(cursor.resource_id, struct virtio_gpu_scanout),
- VMSTATE_UINT32(cursor.hot_x, struct virtio_gpu_scanout),
- VMSTATE_UINT32(cursor.hot_y, struct virtio_gpu_scanout),
- VMSTATE_UINT32(cursor.pos.x, struct virtio_gpu_scanout),
- VMSTATE_UINT32(cursor.pos.y, struct virtio_gpu_scanout),
- VMSTATE_END_OF_LIST()
- },
+static const VMStateDescription vmstate_virtio_gpu_unmigratable = {
+ .name = "virtio-gpu",
+ .unmigratable = 1,
};
-static const VMStateDescription vmstate_virtio_gpu_scanouts = {
- .name = "virtio-gpu-scanouts",
- .version_id = 1,
- .fields = (VMStateField[]) {
- VMSTATE_INT32(enable, struct VirtIOGPU),
- VMSTATE_UINT32_EQUAL(conf.max_outputs, struct VirtIOGPU),
- VMSTATE_STRUCT_VARRAY_UINT32(scanout, struct VirtIOGPU,
- conf.max_outputs, 1,
- vmstate_virtio_gpu_scanout,
- struct virtio_gpu_scanout),
- VMSTATE_END_OF_LIST()
- },
-};
-
-static void virtio_gpu_save(QEMUFile *f, void *opaque, size_t size)
-{
- VirtIOGPU *g = opaque;
- VirtIODevice *vdev = VIRTIO_DEVICE(g);
- struct virtio_gpu_simple_resource *res;
- int i;
-
- virtio_save(vdev, f);
-
- /* in 2d mode we should never find unprocessed commands here */
- assert(QTAILQ_EMPTY(&g->cmdq));
-
- QTAILQ_FOREACH(res, &g->reslist, next) {
- qemu_put_be32(f, res->resource_id);
- qemu_put_be32(f, res->width);
- qemu_put_be32(f, res->height);
- qemu_put_be32(f, res->format);
- qemu_put_be32(f, res->iov_cnt);
- for (i = 0; i < res->iov_cnt; i++) {
- qemu_put_be64(f, res->addrs[i]);
- qemu_put_be32(f, res->iov[i].iov_len);
- }
- qemu_put_buffer(f, (void *)pixman_image_get_data(res->image),
- pixman_image_get_stride(res->image) * res->height);
- }
- qemu_put_be32(f, 0); /* end of list */
-
- vmstate_save_state(f, &vmstate_virtio_gpu_scanouts, g, NULL);
-}
-
-static int virtio_gpu_load(QEMUFile *f, void *opaque, size_t size)
-{
- VirtIOGPU *g = opaque;
- VirtIODevice *vdev = VIRTIO_DEVICE(g);
- struct virtio_gpu_simple_resource *res;
- struct virtio_gpu_scanout *scanout;
- uint32_t resource_id, pformat;
- int i, ret;
-
- ret = virtio_load(vdev, f, VIRTIO_GPU_VM_VERSION);
- if (ret) {
- return ret;
- }
-
- resource_id = qemu_get_be32(f);
- while (resource_id != 0) {
- res = g_new0(struct virtio_gpu_simple_resource, 1);
- res->resource_id = resource_id;
- res->width = qemu_get_be32(f);
- res->height = qemu_get_be32(f);
- res->format = qemu_get_be32(f);
- res->iov_cnt = qemu_get_be32(f);
-
- /* allocate */
- pformat = get_pixman_format(res->format);
- if (!pformat) {
- return -EINVAL;
- }
- res->image = pixman_image_create_bits(pformat,
- res->width, res->height,
- NULL, 0);
- if (!res->image) {
- return -EINVAL;
- }
-
- res->addrs = g_new(uint64_t, res->iov_cnt);
- res->iov = g_new(struct iovec, res->iov_cnt);
-
- /* read data */
- for (i = 0; i < res->iov_cnt; i++) {
- res->addrs[i] = qemu_get_be64(f);
- res->iov[i].iov_len = qemu_get_be32(f);
- }
- qemu_get_buffer(f, (void *)pixman_image_get_data(res->image),
- pixman_image_get_stride(res->image) * res->height);
-
- /* restore mapping */
- for (i = 0; i < res->iov_cnt; i++) {
- hwaddr len = res->iov[i].iov_len;
- res->iov[i].iov_base =
- cpu_physical_memory_map(res->addrs[i], &len, 1);
- if (!res->iov[i].iov_base || len != res->iov[i].iov_len) {
- return -EINVAL;
- }
- }
-
- QTAILQ_INSERT_HEAD(&g->reslist, res, next);
-
- resource_id = qemu_get_be32(f);
- }
-
- /* load & apply scanout state */
- vmstate_load_state(f, &vmstate_virtio_gpu_scanouts, g, 1);
- for (i = 0; i < g->conf.max_outputs; i++) {
- scanout = &g->scanout[i];
- if (!scanout->resource_id) {
- continue;
- }
- res = virtio_gpu_find_resource(g, scanout->resource_id);
- if (!res) {
- return -EINVAL;
- }
- scanout->ds = qemu_create_displaysurface_pixman(res->image);
- if (!scanout->ds) {
- return -EINVAL;
- }
-
- dpy_gfx_replace_surface(scanout->con, scanout->ds);
- dpy_gfx_update(scanout->con, 0, 0, scanout->width, scanout->height);
- update_cursor(g, &scanout->cursor);
- res->scanout_bitmask |= (1 << i);
- }
-
- return 0;
-}
-
static void virtio_gpu_device_realize(DeviceState *qdev, Error **errp)
{
VirtIODevice *vdev = VIRTIO_DEVICE(qdev);
@@ -1110,11 +929,6 @@ static void virtio_gpu_device_realize(DeviceState *qdev, Error **errp)
bool have_virgl;
int i;
- if (g->conf.max_outputs > VIRTIO_GPU_MAX_SCANOUTS) {
- error_setg(errp, "invalid max_outputs > %d", VIRTIO_GPU_MAX_SCANOUTS);
- return;
- }
-
g->config_size = sizeof(struct virtio_gpu_config);
g->virtio_config.num_scanouts = g->conf.max_outputs;
virtio_init(VIRTIO_DEVICE(g), "virtio-gpu", VIRTIO_ID_GPU,
@@ -1160,19 +974,7 @@ static void virtio_gpu_device_realize(DeviceState *qdev, Error **errp)
}
}
- if (virtio_gpu_virgl_enabled(g->conf)) {
- error_setg(&g->migration_blocker, "virgl is not yet migratable");
- migrate_add_blocker(g->migration_blocker);
- }
-}
-
-static void virtio_gpu_device_unrealize(DeviceState *qdev, Error **errp)
-{
- VirtIOGPU *g = VIRTIO_GPU(qdev);
- if (g->migration_blocker) {
- migrate_del_blocker(g->migration_blocker);
- error_free(g->migration_blocker);
- }
+ vmstate_register(qdev, -1, &vmstate_virtio_gpu_unmigratable, g);
}
static void virtio_gpu_instance_init(Object *obj)
@@ -1219,9 +1021,6 @@ static void virtio_gpu_reset(VirtIODevice *vdev)
#endif
}
-VMSTATE_VIRTIO_DEVICE(gpu, VIRTIO_GPU_VM_VERSION, virtio_gpu_load,
- virtio_gpu_save);
-
static Property virtio_gpu_properties[] = {
DEFINE_PROP_UINT32("max_outputs", VirtIOGPU, conf.max_outputs, 1),
#ifdef CONFIG_VIRGL
@@ -1239,7 +1038,6 @@ static void virtio_gpu_class_init(ObjectClass *klass, void *data)
VirtioDeviceClass *vdc = VIRTIO_DEVICE_CLASS(klass);
vdc->realize = virtio_gpu_device_realize;
- vdc->unrealize = virtio_gpu_device_unrealize;
vdc->get_config = virtio_gpu_get_config;
vdc->set_config = virtio_gpu_set_config;
vdc->get_features = virtio_gpu_get_features;
@@ -1248,7 +1046,6 @@ static void virtio_gpu_class_init(ObjectClass *klass, void *data)
vdc->reset = virtio_gpu_reset;
dc->props = virtio_gpu_properties;
- dc->vmsd = &vmstate_virtio_gpu;
}
static const TypeInfo virtio_gpu_info = {
diff --git a/hw/display/virtio-vga.c b/hw/display/virtio-vga.c
index 5b510a17f..e58b165ae 100644
--- a/hw/display/virtio-vga.c
+++ b/hw/display/virtio-vga.c
@@ -4,7 +4,6 @@
#include "ui/console.h"
#include "vga_int.h"
#include "hw/virtio/virtio-pci.h"
-#include "qapi/error.h"
/*
* virtio-vga: This extends VirtioPCIProxy.
@@ -84,24 +83,12 @@ static const GraphicHwOps virtio_vga_ops = {
.gl_block = virtio_vga_gl_block,
};
-static const VMStateDescription vmstate_virtio_vga = {
- .name = "virtio-vga",
- .version_id = 2,
- .minimum_version_id = 2,
- .fields = (VMStateField[]) {
- /* no pci stuff here, saving the virtio device will handle that */
- VMSTATE_STRUCT(vga, VirtIOVGA, 0, vmstate_vga_common, VGACommonState),
- VMSTATE_END_OF_LIST()
- }
-};
-
/* VGA device wrapper around PCI device around virtio GPU */
static void virtio_vga_realize(VirtIOPCIProxy *vpci_dev, Error **errp)
{
VirtIOVGA *vvga = VIRTIO_VGA(vpci_dev);
VirtIOGPU *g = &vvga->vdev;
VGACommonState *vga = &vvga->vga;
- Error *err = NULL;
uint32_t offset;
int i;
@@ -134,12 +121,10 @@ static void virtio_vga_realize(VirtIOPCIProxy *vpci_dev, Error **errp)
/* init virtio bits */
qdev_set_parent_bus(DEVICE(g), BUS(&vpci_dev->bus));
- virtio_pci_force_virtio_1(vpci_dev);
- object_property_set_bool(OBJECT(g), true, "realized", &err);
- if (err) {
- error_propagate(errp, err);
- return;
- }
+ /* force virtio-1.0 */
+ vpci_dev->flags &= ~VIRTIO_PCI_FLAG_DISABLE_MODERN;
+ vpci_dev->flags |= VIRTIO_PCI_FLAG_DISABLE_LEGACY;
+ object_property_set_bool(OBJECT(g), true, "realized", errp);
/* add stdvga mmio regions */
pci_std_vga_mmio_region_init(vga, &vpci_dev->modern_bar,
@@ -177,7 +162,6 @@ static void virtio_vga_class_init(ObjectClass *klass, void *data)
set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
dc->props = virtio_vga_properties;
dc->reset = virtio_vga_reset;
- dc->vmsd = &vmstate_virtio_vga;
dc->hotpluggable = false;
k->realize = virtio_vga_realize;
diff --git a/hw/display/xenfb.c b/hw/display/xenfb.c
index 46b7d5ede..9866dfda5 100644
--- a/hw/display/xenfb.c
+++ b/hw/display/xenfb.c
@@ -25,6 +25,7 @@
*/
#include "qemu/osdep.h"
+#include <sys/mman.h>
#include "hw/hw.h"
#include "ui/console.h"
@@ -471,9 +472,9 @@ static int xenfb_map_fb(struct XenFB *xenfb)
xenfb->pixels = NULL;
}
- xenfb->fbpages = DIV_ROUND_UP(xenfb->fb_len, XC_PAGE_SIZE);
+ xenfb->fbpages = (xenfb->fb_len + (XC_PAGE_SIZE - 1)) / XC_PAGE_SIZE;
n_fbdirs = xenfb->fbpages * mode / 8;
- n_fbdirs = DIV_ROUND_UP(n_fbdirs, XC_PAGE_SIZE);
+ n_fbdirs = (n_fbdirs + (XC_PAGE_SIZE - 1)) / XC_PAGE_SIZE;
pgmfns = g_malloc0(sizeof(xen_pfn_t) * n_fbdirs);
fbmfns = g_malloc0(sizeof(xen_pfn_t) * xenfb->fbpages);
diff --git a/hw/display/xlnx_dp.c b/hw/display/xlnx_dp.c
deleted file mode 100644
index f43eb0930..000000000
--- a/hw/display/xlnx_dp.c
+++ /dev/null
@@ -1,1338 +0,0 @@
-/*
- * xlnx_dp.c
- *
- * Copyright (C) 2015 : GreenSocs Ltd
- * http://www.greensocs.com/ , email: info@greensocs.com
- *
- * Developed by :
- * Frederic Konrad <fred.konrad@greensocs.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 2 of the License, or
- * (at your option)any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, see <http://www.gnu.org/licenses/>.
- *
- */
-
-#include "qemu/osdep.h"
-#include "qemu/log.h"
-#include "hw/display/xlnx_dp.h"
-
-#ifndef DEBUG_DP
-#define DEBUG_DP 0
-#endif
-
-#define DPRINTF(fmt, ...) do { \
- if (DEBUG_DP) { \
- qemu_log("xlnx_dp: " fmt , ## __VA_ARGS__); \
- } \
-} while (0);
-
-/*
- * Register offset for DP.
- */
-#define DP_LINK_BW_SET (0x0000 >> 2)
-#define DP_LANE_COUNT_SET (0x0004 >> 2)
-#define DP_ENHANCED_FRAME_EN (0x0008 >> 2)
-#define DP_TRAINING_PATTERN_SET (0x000C >> 2)
-#define DP_LINK_QUAL_PATTERN_SET (0x0010 >> 2)
-#define DP_SCRAMBLING_DISABLE (0x0014 >> 2)
-#define DP_DOWNSPREAD_CTRL (0x0018 >> 2)
-#define DP_SOFTWARE_RESET (0x001C >> 2)
-#define DP_TRANSMITTER_ENABLE (0x0080 >> 2)
-#define DP_MAIN_STREAM_ENABLE (0x0084 >> 2)
-#define DP_FORCE_SCRAMBLER_RESET (0x00C0 >> 2)
-#define DP_VERSION_REGISTER (0x00F8 >> 2)
-#define DP_CORE_ID (0x00FC >> 2)
-
-#define DP_AUX_COMMAND_REGISTER (0x0100 >> 2)
-#define AUX_ADDR_ONLY_MASK (0x1000)
-#define AUX_COMMAND_MASK (0x0F00)
-#define AUX_COMMAND_SHIFT (8)
-#define AUX_COMMAND_NBYTES (0x000F)
-
-#define DP_AUX_WRITE_FIFO (0x0104 >> 2)
-#define DP_AUX_ADDRESS (0x0108 >> 2)
-#define DP_AUX_CLOCK_DIVIDER (0x010C >> 2)
-#define DP_TX_USER_FIFO_OVERFLOW (0x0110 >> 2)
-#define DP_INTERRUPT_SIGNAL_STATE (0x0130 >> 2)
-#define DP_AUX_REPLY_DATA (0x0134 >> 2)
-#define DP_AUX_REPLY_CODE (0x0138 >> 2)
-#define DP_AUX_REPLY_COUNT (0x013C >> 2)
-#define DP_REPLY_DATA_COUNT (0x0148 >> 2)
-#define DP_REPLY_STATUS (0x014C >> 2)
-#define DP_HPD_DURATION (0x0150 >> 2)
-#define DP_MAIN_STREAM_HTOTAL (0x0180 >> 2)
-#define DP_MAIN_STREAM_VTOTAL (0x0184 >> 2)
-#define DP_MAIN_STREAM_POLARITY (0x0188 >> 2)
-#define DP_MAIN_STREAM_HSWIDTH (0x018C >> 2)
-#define DP_MAIN_STREAM_VSWIDTH (0x0190 >> 2)
-#define DP_MAIN_STREAM_HRES (0x0194 >> 2)
-#define DP_MAIN_STREAM_VRES (0x0198 >> 2)
-#define DP_MAIN_STREAM_HSTART (0x019C >> 2)
-#define DP_MAIN_STREAM_VSTART (0x01A0 >> 2)
-#define DP_MAIN_STREAM_MISC0 (0x01A4 >> 2)
-#define DP_MAIN_STREAM_MISC1 (0x01A8 >> 2)
-#define DP_MAIN_STREAM_M_VID (0x01AC >> 2)
-#define DP_MSA_TRANSFER_UNIT_SIZE (0x01B0 >> 2)
-#define DP_MAIN_STREAM_N_VID (0x01B4 >> 2)
-#define DP_USER_DATA_COUNT_PER_LANE (0x01BC >> 2)
-#define DP_MIN_BYTES_PER_TU (0x01C4 >> 2)
-#define DP_FRAC_BYTES_PER_TU (0x01C8 >> 2)
-#define DP_INIT_WAIT (0x01CC >> 2)
-#define DP_PHY_RESET (0x0200 >> 2)
-#define DP_PHY_VOLTAGE_DIFF_LANE_0 (0x0220 >> 2)
-#define DP_PHY_VOLTAGE_DIFF_LANE_1 (0x0224 >> 2)
-#define DP_TRANSMIT_PRBS7 (0x0230 >> 2)
-#define DP_PHY_CLOCK_SELECT (0x0234 >> 2)
-#define DP_TX_PHY_POWER_DOWN (0x0238 >> 2)
-#define DP_PHY_PRECURSOR_LANE_0 (0x023C >> 2)
-#define DP_PHY_PRECURSOR_LANE_1 (0x0240 >> 2)
-#define DP_PHY_POSTCURSOR_LANE_0 (0x024C >> 2)
-#define DP_PHY_POSTCURSOR_LANE_1 (0x0250 >> 2)
-#define DP_PHY_STATUS (0x0280 >> 2)
-
-#define DP_TX_AUDIO_CONTROL (0x0300 >> 2)
-#define DP_TX_AUD_CTRL (1)
-
-#define DP_TX_AUDIO_CHANNELS (0x0304 >> 2)
-#define DP_TX_AUDIO_INFO_DATA(n) ((0x0308 + 4 * n) >> 2)
-#define DP_TX_M_AUD (0x0328 >> 2)
-#define DP_TX_N_AUD (0x032C >> 2)
-#define DP_TX_AUDIO_EXT_DATA(n) ((0x0330 + 4 * n) >> 2)
-#define DP_INT_STATUS (0x03A0 >> 2)
-#define DP_INT_MASK (0x03A4 >> 2)
-#define DP_INT_EN (0x03A8 >> 2)
-#define DP_INT_DS (0x03AC >> 2)
-
-/*
- * Registers offset for Audio Video Buffer configuration.
- */
-#define V_BLEND_OFFSET (0xA000)
-#define V_BLEND_BG_CLR_0 (0x0000 >> 2)
-#define V_BLEND_BG_CLR_1 (0x0004 >> 2)
-#define V_BLEND_BG_CLR_2 (0x0008 >> 2)
-#define V_BLEND_SET_GLOBAL_ALPHA_REG (0x000C >> 2)
-#define V_BLEND_OUTPUT_VID_FORMAT (0x0014 >> 2)
-#define V_BLEND_LAYER0_CONTROL (0x0018 >> 2)
-#define V_BLEND_LAYER1_CONTROL (0x001C >> 2)
-
-#define V_BLEND_RGB2YCBCR_COEFF(n) ((0x0020 + 4 * n) >> 2)
-#define V_BLEND_IN1CSC_COEFF(n) ((0x0044 + 4 * n) >> 2)
-
-#define V_BLEND_LUMA_IN1CSC_OFFSET (0x0068 >> 2)
-#define V_BLEND_CR_IN1CSC_OFFSET (0x006C >> 2)
-#define V_BLEND_CB_IN1CSC_OFFSET (0x0070 >> 2)
-#define V_BLEND_LUMA_OUTCSC_OFFSET (0x0074 >> 2)
-#define V_BLEND_CR_OUTCSC_OFFSET (0x0078 >> 2)
-#define V_BLEND_CB_OUTCSC_OFFSET (0x007C >> 2)
-
-#define V_BLEND_IN2CSC_COEFF(n) ((0x0080 + 4 * n) >> 2)
-
-#define V_BLEND_LUMA_IN2CSC_OFFSET (0x00A4 >> 2)
-#define V_BLEND_CR_IN2CSC_OFFSET (0x00A8 >> 2)
-#define V_BLEND_CB_IN2CSC_OFFSET (0x00AC >> 2)
-#define V_BLEND_CHROMA_KEY_ENABLE (0x01D0 >> 2)
-#define V_BLEND_CHROMA_KEY_COMP1 (0x01D4 >> 2)
-#define V_BLEND_CHROMA_KEY_COMP2 (0x01D8 >> 2)
-#define V_BLEND_CHROMA_KEY_COMP3 (0x01DC >> 2)
-
-/*
- * Registers offset for Audio Video Buffer configuration.
- */
-#define AV_BUF_MANAGER_OFFSET (0xB000)
-#define AV_BUF_FORMAT (0x0000 >> 2)
-#define AV_BUF_NON_LIVE_LATENCY (0x0008 >> 2)
-#define AV_CHBUF0 (0x0010 >> 2)
-#define AV_CHBUF1 (0x0014 >> 2)
-#define AV_CHBUF2 (0x0018 >> 2)
-#define AV_CHBUF3 (0x001C >> 2)
-#define AV_CHBUF4 (0x0020 >> 2)
-#define AV_CHBUF5 (0x0024 >> 2)
-#define AV_BUF_STC_CONTROL (0x002C >> 2)
-#define AV_BUF_STC_INIT_VALUE0 (0x0030 >> 2)
-#define AV_BUF_STC_INIT_VALUE1 (0x0034 >> 2)
-#define AV_BUF_STC_ADJ (0x0038 >> 2)
-#define AV_BUF_STC_VIDEO_VSYNC_TS_REG0 (0x003C >> 2)
-#define AV_BUF_STC_VIDEO_VSYNC_TS_REG1 (0x0040 >> 2)
-#define AV_BUF_STC_EXT_VSYNC_TS_REG0 (0x0044 >> 2)
-#define AV_BUF_STC_EXT_VSYNC_TS_REG1 (0x0048 >> 2)
-#define AV_BUF_STC_CUSTOM_EVENT_TS_REG0 (0x004C >> 2)
-#define AV_BUF_STC_CUSTOM_EVENT_TS_REG1 (0x0050 >> 2)
-#define AV_BUF_STC_CUSTOM_EVENT2_TS_REG0 (0x0054 >> 2)
-#define AV_BUF_STC_CUSTOM_EVENT2_TS_REG1 (0x0058 >> 2)
-#define AV_BUF_STC_SNAPSHOT0 (0x0060 >> 2)
-#define AV_BUF_STC_SNAPSHOT1 (0x0064 >> 2)
-#define AV_BUF_OUTPUT_AUDIO_VIDEO_SELECT (0x0070 >> 2)
-#define AV_BUF_HCOUNT_VCOUNT_INT0 (0x0074 >> 2)
-#define AV_BUF_HCOUNT_VCOUNT_INT1 (0x0078 >> 2)
-#define AV_BUF_DITHER_CONFIG (0x007C >> 2)
-#define AV_BUF_DITHER_CONFIG_MAX (0x008C >> 2)
-#define AV_BUF_DITHER_CONFIG_MIN (0x0090 >> 2)
-#define AV_BUF_PATTERN_GEN_SELECT (0x0100 >> 2)
-#define AV_BUF_AUD_VID_CLK_SOURCE (0x0120 >> 2)
-#define AV_BUF_SRST_REG (0x0124 >> 2)
-#define AV_BUF_AUDIO_RDY_INTERVAL (0x0128 >> 2)
-#define AV_BUF_AUDIO_CH_CONFIG (0x012C >> 2)
-
-#define AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(n)((0x0200 + 4 * n) >> 2)
-
-#define AV_BUF_VIDEO_COMP_SCALE_FACTOR(n) ((0x020C + 4 * n) >> 2)
-
-#define AV_BUF_LIVE_VIDEO_COMP_SF(n) ((0x0218 + 4 * n) >> 2)
-
-#define AV_BUF_LIVE_VID_CONFIG (0x0224 >> 2)
-
-#define AV_BUF_LIVE_GFX_COMP_SF(n) ((0x0228 + 4 * n) >> 2)
-
-#define AV_BUF_LIVE_GFX_CONFIG (0x0234 >> 2)
-
-#define AUDIO_MIXER_REGISTER_OFFSET (0xC000)
-#define AUDIO_MIXER_VOLUME_CONTROL (0x0000 >> 2)
-#define AUDIO_MIXER_META_DATA (0x0004 >> 2)
-#define AUD_CH_STATUS_REG(n) ((0x0008 + 4 * n) >> 2)
-#define AUD_CH_A_DATA_REG(n) ((0x0020 + 4 * n) >> 2)
-#define AUD_CH_B_DATA_REG(n) ((0x0038 + 4 * n) >> 2)
-
-#define DP_AUDIO_DMA_CHANNEL(n) (4 + n)
-#define DP_GRAPHIC_DMA_CHANNEL (3)
-#define DP_VIDEO_DMA_CHANNEL (0)
-
-enum DPGraphicFmt {
- DP_GRAPHIC_RGBA8888 = 0 << 8,
- DP_GRAPHIC_ABGR8888 = 1 << 8,
- DP_GRAPHIC_RGB888 = 2 << 8,
- DP_GRAPHIC_BGR888 = 3 << 8,
- DP_GRAPHIC_RGBA5551 = 4 << 8,
- DP_GRAPHIC_RGBA4444 = 5 << 8,
- DP_GRAPHIC_RGB565 = 6 << 8,
- DP_GRAPHIC_8BPP = 7 << 8,
- DP_GRAPHIC_4BPP = 8 << 8,
- DP_GRAPHIC_2BPP = 9 << 8,
- DP_GRAPHIC_1BPP = 10 << 8,
- DP_GRAPHIC_MASK = 0xF << 8
-};
-
-enum DPVideoFmt {
- DP_NL_VID_CB_Y0_CR_Y1 = 0,
- DP_NL_VID_CR_Y0_CB_Y1 = 1,
- DP_NL_VID_Y0_CR_Y1_CB = 2,
- DP_NL_VID_Y0_CB_Y1_CR = 3,
- DP_NL_VID_YV16 = 4,
- DP_NL_VID_YV24 = 5,
- DP_NL_VID_YV16CL = 6,
- DP_NL_VID_MONO = 7,
- DP_NL_VID_YV16CL2 = 8,
- DP_NL_VID_YUV444 = 9,
- DP_NL_VID_RGB888 = 10,
- DP_NL_VID_RGBA8880 = 11,
- DP_NL_VID_RGB888_10BPC = 12,
- DP_NL_VID_YUV444_10BPC = 13,
- DP_NL_VID_YV16CL2_10BPC = 14,
- DP_NL_VID_YV16CL_10BPC = 15,
- DP_NL_VID_YV16_10BPC = 16,
- DP_NL_VID_YV24_10BPC = 17,
- DP_NL_VID_Y_ONLY_10BPC = 18,
- DP_NL_VID_YV16_420 = 19,
- DP_NL_VID_YV16CL_420 = 20,
- DP_NL_VID_YV16CL2_420 = 21,
- DP_NL_VID_YV16_420_10BPC = 22,
- DP_NL_VID_YV16CL_420_10BPC = 23,
- DP_NL_VID_YV16CL2_420_10BPC = 24,
- DP_NL_VID_FMT_MASK = 0x1F
-};
-
-typedef enum DPGraphicFmt DPGraphicFmt;
-typedef enum DPVideoFmt DPVideoFmt;
-
-static const VMStateDescription vmstate_dp = {
- .name = TYPE_XLNX_DP,
- .version_id = 1,
- .fields = (VMStateField[]){
- VMSTATE_UINT32_ARRAY(core_registers, XlnxDPState,
- DP_CORE_REG_ARRAY_SIZE),
- VMSTATE_UINT32_ARRAY(avbufm_registers, XlnxDPState,
- DP_AVBUF_REG_ARRAY_SIZE),
- VMSTATE_UINT32_ARRAY(vblend_registers, XlnxDPState,
- DP_VBLEND_REG_ARRAY_SIZE),
- VMSTATE_UINT32_ARRAY(audio_registers, XlnxDPState,
- DP_AUDIO_REG_ARRAY_SIZE),
- VMSTATE_END_OF_LIST()
- }
-};
-
-static void xlnx_dp_update_irq(XlnxDPState *s);
-
-static uint64_t xlnx_dp_audio_read(void *opaque, hwaddr offset, unsigned size)
-{
- XlnxDPState *s = XLNX_DP(opaque);
-
- offset = offset >> 2;
- return s->audio_registers[offset];
-}
-
-static void xlnx_dp_audio_write(void *opaque, hwaddr offset, uint64_t value,
- unsigned size)
-{
- XlnxDPState *s = XLNX_DP(opaque);
-
- offset = offset >> 2;
-
- switch (offset) {
- case AUDIO_MIXER_META_DATA:
- s->audio_registers[offset] = value & 0x00000001;
- break;
- default:
- s->audio_registers[offset] = value;
- break;
- }
-}
-
-static const MemoryRegionOps audio_ops = {
- .read = xlnx_dp_audio_read,
- .write = xlnx_dp_audio_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
-};
-
-static inline uint32_t xlnx_dp_audio_get_volume(XlnxDPState *s,
- uint8_t channel)
-{
- switch (channel) {
- case 0:
- return extract32(s->audio_registers[AUDIO_MIXER_VOLUME_CONTROL], 0, 16);
- case 1:
- return extract32(s->audio_registers[AUDIO_MIXER_VOLUME_CONTROL], 16,
- 16);
- default:
- return 0;
- }
-}
-
-static inline void xlnx_dp_audio_activate(XlnxDPState *s)
-{
- bool activated = ((s->core_registers[DP_TX_AUDIO_CONTROL]
- & DP_TX_AUD_CTRL) != 0);
- AUD_set_active_out(s->amixer_output_stream, activated);
- xlnx_dpdma_set_host_data_location(s->dpdma, DP_AUDIO_DMA_CHANNEL(0),
- &s->audio_buffer_0);
- xlnx_dpdma_set_host_data_location(s->dpdma, DP_AUDIO_DMA_CHANNEL(1),
- &s->audio_buffer_1);
-}
-
-static inline void xlnx_dp_audio_mix_buffer(XlnxDPState *s)
-{
- /*
- * Audio packets are signed and have this shape:
- * | 16 | 16 | 16 | 16 | 16 | 16 | 16 | 16 |
- * | R3 | L3 | R2 | L2 | R1 | L1 | R0 | L0 |
- *
- * Output audio is 16bits saturated.
- */
- int i;
-
- if ((s->audio_data_available[0]) && (xlnx_dp_audio_get_volume(s, 0))) {
- for (i = 0; i < s->audio_data_available[0] / 2; i++) {
- s->temp_buffer[i] = (int64_t)(s->audio_buffer_0[i])
- * xlnx_dp_audio_get_volume(s, 0) / 8192;
- }
- s->byte_left = s->audio_data_available[0];
- } else {
- memset(s->temp_buffer, 0, s->audio_data_available[1] / 2);
- }
-
- if ((s->audio_data_available[1]) && (xlnx_dp_audio_get_volume(s, 1))) {
- if ((s->audio_data_available[0] == 0)
- || (s->audio_data_available[1] == s->audio_data_available[0])) {
- for (i = 0; i < s->audio_data_available[1] / 2; i++) {
- s->temp_buffer[i] += (int64_t)(s->audio_buffer_1[i])
- * xlnx_dp_audio_get_volume(s, 1) / 8192;
- }
- s->byte_left = s->audio_data_available[1];
- }
- }
-
- for (i = 0; i < s->byte_left / 2; i++) {
- s->out_buffer[i] = MAX(-32767, MIN(s->temp_buffer[i], 32767));
- }
-
- s->data_ptr = 0;
-}
-
-static void xlnx_dp_audio_callback(void *opaque, int avail)
-{
- /*
- * Get some data from the DPDMA and compute these datas.
- * Then wait for QEMU's audio subsystem to call this callback.
- */
- XlnxDPState *s = XLNX_DP(opaque);
- size_t written = 0;
-
- /* If there are already some data don't get more data. */
- if (s->byte_left == 0) {
- s->audio_data_available[0] = xlnx_dpdma_start_operation(s->dpdma, 4,
- true);
- s->audio_data_available[1] = xlnx_dpdma_start_operation(s->dpdma, 5,
- true);
- xlnx_dp_audio_mix_buffer(s);
- }
-
- /* Send the buffer through the audio. */
- if (s->byte_left <= MAX_QEMU_BUFFER_SIZE) {
- if (s->byte_left != 0) {
- written = AUD_write(s->amixer_output_stream,
- &s->out_buffer[s->data_ptr], s->byte_left);
- } else {
- /*
- * There is nothing to play.. We don't have any data! Fill the
- * buffer with zero's and send it.
- */
- written = 0;
- memset(s->out_buffer, 0, 1024);
- AUD_write(s->amixer_output_stream, s->out_buffer, 1024);
- }
- } else {
- written = AUD_write(s->amixer_output_stream,
- &s->out_buffer[s->data_ptr], MAX_QEMU_BUFFER_SIZE);
- }
- s->byte_left -= written;
- s->data_ptr += written;
-}
-
-/*
- * AUX channel related function.
- */
-static void xlnx_dp_aux_clear_rx_fifo(XlnxDPState *s)
-{
- fifo8_reset(&s->rx_fifo);
-}
-
-static void xlnx_dp_aux_push_rx_fifo(XlnxDPState *s, uint8_t *buf, size_t len)
-{
- DPRINTF("Push %u data in rx_fifo\n", (unsigned)len);
- fifo8_push_all(&s->rx_fifo, buf, len);
-}
-
-static uint8_t xlnx_dp_aux_pop_rx_fifo(XlnxDPState *s)
-{
- uint8_t ret;
-
- if (fifo8_is_empty(&s->rx_fifo)) {
- DPRINTF("rx_fifo underflow..\n");
- abort();
- }
- ret = fifo8_pop(&s->rx_fifo);
- DPRINTF("pop 0x%" PRIX8 " from rx_fifo.\n", ret);
- return ret;
-}
-
-static void xlnx_dp_aux_clear_tx_fifo(XlnxDPState *s)
-{
- fifo8_reset(&s->tx_fifo);
-}
-
-static void xlnx_dp_aux_push_tx_fifo(XlnxDPState *s, uint8_t *buf, size_t len)
-{
- DPRINTF("Push %u data in tx_fifo\n", (unsigned)len);
- fifo8_push_all(&s->tx_fifo, buf, len);
-}
-
-static uint8_t xlnx_dp_aux_pop_tx_fifo(XlnxDPState *s)
-{
- uint8_t ret;
-
- if (fifo8_is_empty(&s->tx_fifo)) {
- DPRINTF("tx_fifo underflow..\n");
- abort();
- }
- ret = fifo8_pop(&s->tx_fifo);
- DPRINTF("pop 0x%2.2X from tx_fifo.\n", ret);
- return ret;
-}
-
-static uint32_t xlnx_dp_aux_get_address(XlnxDPState *s)
-{
- return s->core_registers[DP_AUX_ADDRESS];
-}
-
-/*
- * Get command from the register.
- */
-static void xlnx_dp_aux_set_command(XlnxDPState *s, uint32_t value)
-{
- bool address_only = (value & AUX_ADDR_ONLY_MASK) != 0;
- AUXCommand cmd = (value & AUX_COMMAND_MASK) >> AUX_COMMAND_SHIFT;
- uint8_t nbytes = (value & AUX_COMMAND_NBYTES) + 1;
- uint8_t buf[16];
- int i;
-
- /*
- * When an address_only command is executed nothing happen to the fifo, so
- * just make nbytes = 0.
- */
- if (address_only) {
- nbytes = 0;
- }
-
- switch (cmd) {
- case READ_AUX:
- case READ_I2C:
- case READ_I2C_MOT:
- s->core_registers[DP_AUX_REPLY_CODE] = aux_request(s->aux_bus, cmd,
- xlnx_dp_aux_get_address(s),
- nbytes, buf);
- s->core_registers[DP_REPLY_DATA_COUNT] = nbytes;
-
- if (s->core_registers[DP_AUX_REPLY_CODE] == AUX_I2C_ACK) {
- xlnx_dp_aux_push_rx_fifo(s, buf, nbytes);
- }
- break;
- case WRITE_AUX:
- case WRITE_I2C:
- case WRITE_I2C_MOT:
- for (i = 0; i < nbytes; i++) {
- buf[i] = xlnx_dp_aux_pop_tx_fifo(s);
- }
- s->core_registers[DP_AUX_REPLY_CODE] = aux_request(s->aux_bus, cmd,
- xlnx_dp_aux_get_address(s),
- nbytes, buf);
- xlnx_dp_aux_clear_tx_fifo(s);
- break;
- case WRITE_I2C_STATUS:
- qemu_log_mask(LOG_UNIMP, "xlnx_dp: Write i2c status not implemented\n");
- break;
- default:
- abort();
- }
-
- s->core_registers[DP_INTERRUPT_SIGNAL_STATE] |= 0x04;
-}
-
-static void xlnx_dp_set_dpdma(Object *obj, const char *name, Object *val,
- Error **errp)
-{
- XlnxDPState *s = XLNX_DP(obj);
- if (s->console) {
- DisplaySurface *surface = qemu_console_surface(s->console);
- XlnxDPDMAState *dma = XLNX_DPDMA(val);
- xlnx_dpdma_set_host_data_location(dma, DP_GRAPHIC_DMA_CHANNEL,
- surface_data(surface));
- }
-}
-
-static inline uint8_t xlnx_dp_global_alpha_value(XlnxDPState *s)
-{
- return (s->vblend_registers[V_BLEND_SET_GLOBAL_ALPHA_REG] & 0x1FE) >> 1;
-}
-
-static inline bool xlnx_dp_global_alpha_enabled(XlnxDPState *s)
-{
- /*
- * If the alpha is totally opaque (255) we consider the alpha is disabled to
- * reduce CPU consumption.
- */
- return ((xlnx_dp_global_alpha_value(s) != 0xFF) &&
- ((s->vblend_registers[V_BLEND_SET_GLOBAL_ALPHA_REG] & 0x01) != 0));
-}
-
-static void xlnx_dp_recreate_surface(XlnxDPState *s)
-{
- /*
- * Two possibilities, if blending is enabled the console displays
- * bout_plane, if not g_plane is displayed.
- */
- uint16_t width = s->core_registers[DP_MAIN_STREAM_HRES];
- uint16_t height = s->core_registers[DP_MAIN_STREAM_VRES];
- DisplaySurface *current_console_surface = qemu_console_surface(s->console);
-
- if ((width != 0) && (height != 0)) {
- /*
- * As dpy_gfx_replace_surface calls qemu_free_displaysurface on the
- * surface we need to be carefull and don't free the surface associated
- * to the console or double free will happen.
- */
- if (s->bout_plane.surface != current_console_surface) {
- qemu_free_displaysurface(s->bout_plane.surface);
- }
- if (s->v_plane.surface != current_console_surface) {
- qemu_free_displaysurface(s->v_plane.surface);
- }
- if (s->g_plane.surface != current_console_surface) {
- qemu_free_displaysurface(s->g_plane.surface);
- }
-
- s->g_plane.surface
- = qemu_create_displaysurface_from(width, height,
- s->g_plane.format, 0, NULL);
- s->v_plane.surface
- = qemu_create_displaysurface_from(width, height,
- s->v_plane.format, 0, NULL);
- if (xlnx_dp_global_alpha_enabled(s)) {
- s->bout_plane.surface =
- qemu_create_displaysurface_from(width,
- height,
- s->g_plane.format,
- 0, NULL);
- dpy_gfx_replace_surface(s->console, s->bout_plane.surface);
- } else {
- s->bout_plane.surface = NULL;
- dpy_gfx_replace_surface(s->console, s->g_plane.surface);
- }
-
- xlnx_dpdma_set_host_data_location(s->dpdma, DP_GRAPHIC_DMA_CHANNEL,
- surface_data(s->g_plane.surface));
- xlnx_dpdma_set_host_data_location(s->dpdma, DP_VIDEO_DMA_CHANNEL,
- surface_data(s->v_plane.surface));
- }
-}
-
-/*
- * Change the graphic format of the surface.
- */
-static void xlnx_dp_change_graphic_fmt(XlnxDPState *s)
-{
- switch (s->avbufm_registers[AV_BUF_FORMAT] & DP_GRAPHIC_MASK) {
- case DP_GRAPHIC_RGBA8888:
- s->g_plane.format = PIXMAN_r8g8b8a8;
- break;
- case DP_GRAPHIC_ABGR8888:
- s->g_plane.format = PIXMAN_a8b8g8r8;
- break;
- case DP_GRAPHIC_RGB565:
- s->g_plane.format = PIXMAN_r5g6b5;
- break;
- case DP_GRAPHIC_RGB888:
- s->g_plane.format = PIXMAN_r8g8b8;
- break;
- case DP_GRAPHIC_BGR888:
- s->g_plane.format = PIXMAN_b8g8r8;
- break;
- default:
- DPRINTF("error: unsupported graphic format %u.\n",
- s->avbufm_registers[AV_BUF_FORMAT] & DP_GRAPHIC_MASK);
- abort();
- }
-
- switch (s->avbufm_registers[AV_BUF_FORMAT] & DP_NL_VID_FMT_MASK) {
- case 0:
- s->v_plane.format = PIXMAN_x8b8g8r8;
- break;
- case DP_NL_VID_RGBA8880:
- s->v_plane.format = PIXMAN_x8b8g8r8;
- break;
- default:
- DPRINTF("error: unsupported video format %u.\n",
- s->avbufm_registers[AV_BUF_FORMAT] & DP_NL_VID_FMT_MASK);
- abort();
- }
-
- xlnx_dp_recreate_surface(s);
-}
-
-static void xlnx_dp_update_irq(XlnxDPState *s)
-{
- uint32_t flags;
-
- flags = s->core_registers[DP_INT_STATUS] & ~s->core_registers[DP_INT_MASK];
- DPRINTF("update IRQ value = %" PRIx32 "\n", flags);
- qemu_set_irq(s->irq, flags != 0);
-}
-
-static uint64_t xlnx_dp_read(void *opaque, hwaddr offset, unsigned size)
-{
- XlnxDPState *s = XLNX_DP(opaque);
- uint64_t ret = 0;
-
- offset = offset >> 2;
-
- switch (offset) {
- case DP_TX_USER_FIFO_OVERFLOW:
- /* This register is cleared after a read */
- ret = s->core_registers[DP_TX_USER_FIFO_OVERFLOW];
- s->core_registers[DP_TX_USER_FIFO_OVERFLOW] = 0;
- break;
- case DP_AUX_REPLY_DATA:
- ret = xlnx_dp_aux_pop_rx_fifo(s);
- break;
- case DP_INTERRUPT_SIGNAL_STATE:
- /*
- * XXX: Not sure it is the right thing to do actually.
- * The register is not written by the device driver so it's stuck
- * to 0x04.
- */
- ret = s->core_registers[DP_INTERRUPT_SIGNAL_STATE];
- s->core_registers[DP_INTERRUPT_SIGNAL_STATE] &= ~0x04;
- break;
- case DP_AUX_WRITE_FIFO:
- case DP_TX_AUDIO_INFO_DATA(0):
- case DP_TX_AUDIO_INFO_DATA(1):
- case DP_TX_AUDIO_INFO_DATA(2):
- case DP_TX_AUDIO_INFO_DATA(3):
- case DP_TX_AUDIO_INFO_DATA(4):
- case DP_TX_AUDIO_INFO_DATA(5):
- case DP_TX_AUDIO_INFO_DATA(6):
- case DP_TX_AUDIO_INFO_DATA(7):
- case DP_TX_AUDIO_EXT_DATA(0):
- case DP_TX_AUDIO_EXT_DATA(1):
- case DP_TX_AUDIO_EXT_DATA(2):
- case DP_TX_AUDIO_EXT_DATA(3):
- case DP_TX_AUDIO_EXT_DATA(4):
- case DP_TX_AUDIO_EXT_DATA(5):
- case DP_TX_AUDIO_EXT_DATA(6):
- case DP_TX_AUDIO_EXT_DATA(7):
- case DP_TX_AUDIO_EXT_DATA(8):
- /* write only registers */
- ret = 0;
- break;
- default:
- assert(offset <= (0x3AC >> 2));
- ret = s->core_registers[offset];
- break;
- }
-
- DPRINTF("core read @%" PRIx64 " = 0x%8.8" PRIX64 "\n", offset << 2, ret);
- return ret;
-}
-
-static void xlnx_dp_write(void *opaque, hwaddr offset, uint64_t value,
- unsigned size)
-{
- XlnxDPState *s = XLNX_DP(opaque);
-
- DPRINTF("core write @%" PRIx64 " = 0x%8.8" PRIX64 "\n", offset, value);
-
- offset = offset >> 2;
-
- switch (offset) {
- /*
- * Only special write case are handled.
- */
- case DP_LINK_BW_SET:
- s->core_registers[offset] = value & 0x000000FF;
- break;
- case DP_LANE_COUNT_SET:
- case DP_MAIN_STREAM_MISC0:
- s->core_registers[offset] = value & 0x0000000F;
- break;
- case DP_TRAINING_PATTERN_SET:
- case DP_LINK_QUAL_PATTERN_SET:
- case DP_MAIN_STREAM_POLARITY:
- case DP_PHY_VOLTAGE_DIFF_LANE_0:
- case DP_PHY_VOLTAGE_DIFF_LANE_1:
- s->core_registers[offset] = value & 0x00000003;
- break;
- case DP_ENHANCED_FRAME_EN:
- case DP_SCRAMBLING_DISABLE:
- case DP_DOWNSPREAD_CTRL:
- case DP_MAIN_STREAM_ENABLE:
- case DP_TRANSMIT_PRBS7:
- s->core_registers[offset] = value & 0x00000001;
- break;
- case DP_PHY_CLOCK_SELECT:
- s->core_registers[offset] = value & 0x00000007;
- break;
- case DP_SOFTWARE_RESET:
- /*
- * No need to update this bit as it's read '0'.
- */
- /*
- * TODO: reset IP.
- */
- break;
- case DP_TRANSMITTER_ENABLE:
- s->core_registers[offset] = value & 0x01;
- break;
- case DP_FORCE_SCRAMBLER_RESET:
- /*
- * No need to update this bit as it's read '0'.
- */
- /*
- * TODO: force a scrambler reset??
- */
- break;
- case DP_AUX_COMMAND_REGISTER:
- s->core_registers[offset] = value & 0x00001F0F;
- xlnx_dp_aux_set_command(s, s->core_registers[offset]);
- break;
- case DP_MAIN_STREAM_HTOTAL:
- case DP_MAIN_STREAM_VTOTAL:
- case DP_MAIN_STREAM_HSTART:
- case DP_MAIN_STREAM_VSTART:
- s->core_registers[offset] = value & 0x0000FFFF;
- break;
- case DP_MAIN_STREAM_HRES:
- case DP_MAIN_STREAM_VRES:
- s->core_registers[offset] = value & 0x0000FFFF;
- xlnx_dp_recreate_surface(s);
- break;
- case DP_MAIN_STREAM_HSWIDTH:
- case DP_MAIN_STREAM_VSWIDTH:
- s->core_registers[offset] = value & 0x00007FFF;
- break;
- case DP_MAIN_STREAM_MISC1:
- s->core_registers[offset] = value & 0x00000086;
- break;
- case DP_MAIN_STREAM_M_VID:
- case DP_MAIN_STREAM_N_VID:
- s->core_registers[offset] = value & 0x00FFFFFF;
- break;
- case DP_MSA_TRANSFER_UNIT_SIZE:
- case DP_MIN_BYTES_PER_TU:
- case DP_INIT_WAIT:
- s->core_registers[offset] = value & 0x00000007;
- break;
- case DP_USER_DATA_COUNT_PER_LANE:
- s->core_registers[offset] = value & 0x0003FFFF;
- break;
- case DP_FRAC_BYTES_PER_TU:
- s->core_registers[offset] = value & 0x000003FF;
- break;
- case DP_PHY_RESET:
- s->core_registers[offset] = value & 0x00010003;
- /*
- * TODO: Reset something?
- */
- break;
- case DP_TX_PHY_POWER_DOWN:
- s->core_registers[offset] = value & 0x0000000F;
- /*
- * TODO: Power down things?
- */
- break;
- case DP_AUX_WRITE_FIFO: {
- uint8_t c = value;
- xlnx_dp_aux_push_tx_fifo(s, &c, 1);
- break;
- }
- case DP_AUX_CLOCK_DIVIDER:
- break;
- case DP_AUX_REPLY_COUNT:
- /*
- * Writing to this register clear the counter.
- */
- s->core_registers[offset] = 0x00000000;
- break;
- case DP_AUX_ADDRESS:
- s->core_registers[offset] = value & 0x000FFFFF;
- break;
- case DP_VERSION_REGISTER:
- case DP_CORE_ID:
- case DP_TX_USER_FIFO_OVERFLOW:
- case DP_AUX_REPLY_DATA:
- case DP_AUX_REPLY_CODE:
- case DP_REPLY_DATA_COUNT:
- case DP_REPLY_STATUS:
- case DP_HPD_DURATION:
- /*
- * Write to read only location..
- */
- break;
- case DP_TX_AUDIO_CONTROL:
- s->core_registers[offset] = value & 0x00000001;
- xlnx_dp_audio_activate(s);
- break;
- case DP_TX_AUDIO_CHANNELS:
- s->core_registers[offset] = value & 0x00000007;
- xlnx_dp_audio_activate(s);
- break;
- case DP_INT_STATUS:
- s->core_registers[DP_INT_STATUS] &= ~value;
- xlnx_dp_update_irq(s);
- break;
- case DP_INT_EN:
- s->core_registers[DP_INT_MASK] &= ~value;
- xlnx_dp_update_irq(s);
- break;
- case DP_INT_DS:
- s->core_registers[DP_INT_MASK] |= ~value;
- xlnx_dp_update_irq(s);
- break;
- default:
- assert(offset <= (0x504C >> 2));
- s->core_registers[offset] = value;
- break;
- }
-}
-
-static const MemoryRegionOps dp_ops = {
- .read = xlnx_dp_read,
- .write = xlnx_dp_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
- .valid = {
- .min_access_size = 4,
- .max_access_size = 4,
- },
- .impl = {
- .min_access_size = 4,
- .max_access_size = 4,
- },
-};
-
-/*
- * This is to handle Read/Write to the Video Blender.
- */
-static void xlnx_dp_vblend_write(void *opaque, hwaddr offset,
- uint64_t value, unsigned size)
-{
- XlnxDPState *s = XLNX_DP(opaque);
- bool alpha_was_enabled;
-
- DPRINTF("vblend: write @0x%" HWADDR_PRIX " = 0x%" PRIX32 "\n", offset,
- (uint32_t)value);
- offset = offset >> 2;
-
- switch (offset) {
- case V_BLEND_BG_CLR_0:
- case V_BLEND_BG_CLR_1:
- case V_BLEND_BG_CLR_2:
- s->vblend_registers[offset] = value & 0x00000FFF;
- break;
- case V_BLEND_SET_GLOBAL_ALPHA_REG:
- /*
- * A write to this register can enable or disable blending. Thus we need
- * to recreate the surfaces.
- */
- alpha_was_enabled = xlnx_dp_global_alpha_enabled(s);
- s->vblend_registers[offset] = value & 0x000001FF;
- if (xlnx_dp_global_alpha_enabled(s) != alpha_was_enabled) {
- xlnx_dp_recreate_surface(s);
- }
- break;
- case V_BLEND_OUTPUT_VID_FORMAT:
- s->vblend_registers[offset] = value & 0x00000017;
- break;
- case V_BLEND_LAYER0_CONTROL:
- case V_BLEND_LAYER1_CONTROL:
- s->vblend_registers[offset] = value & 0x00000103;
- break;
- case V_BLEND_RGB2YCBCR_COEFF(0):
- case V_BLEND_RGB2YCBCR_COEFF(1):
- case V_BLEND_RGB2YCBCR_COEFF(2):
- case V_BLEND_RGB2YCBCR_COEFF(3):
- case V_BLEND_RGB2YCBCR_COEFF(4):
- case V_BLEND_RGB2YCBCR_COEFF(5):
- case V_BLEND_RGB2YCBCR_COEFF(6):
- case V_BLEND_RGB2YCBCR_COEFF(7):
- case V_BLEND_RGB2YCBCR_COEFF(8):
- case V_BLEND_IN1CSC_COEFF(0):
- case V_BLEND_IN1CSC_COEFF(1):
- case V_BLEND_IN1CSC_COEFF(2):
- case V_BLEND_IN1CSC_COEFF(3):
- case V_BLEND_IN1CSC_COEFF(4):
- case V_BLEND_IN1CSC_COEFF(5):
- case V_BLEND_IN1CSC_COEFF(6):
- case V_BLEND_IN1CSC_COEFF(7):
- case V_BLEND_IN1CSC_COEFF(8):
- case V_BLEND_IN2CSC_COEFF(0):
- case V_BLEND_IN2CSC_COEFF(1):
- case V_BLEND_IN2CSC_COEFF(2):
- case V_BLEND_IN2CSC_COEFF(3):
- case V_BLEND_IN2CSC_COEFF(4):
- case V_BLEND_IN2CSC_COEFF(5):
- case V_BLEND_IN2CSC_COEFF(6):
- case V_BLEND_IN2CSC_COEFF(7):
- case V_BLEND_IN2CSC_COEFF(8):
- s->vblend_registers[offset] = value & 0x0000FFFF;
- break;
- case V_BLEND_LUMA_IN1CSC_OFFSET:
- case V_BLEND_CR_IN1CSC_OFFSET:
- case V_BLEND_CB_IN1CSC_OFFSET:
- case V_BLEND_LUMA_IN2CSC_OFFSET:
- case V_BLEND_CR_IN2CSC_OFFSET:
- case V_BLEND_CB_IN2CSC_OFFSET:
- case V_BLEND_LUMA_OUTCSC_OFFSET:
- case V_BLEND_CR_OUTCSC_OFFSET:
- case V_BLEND_CB_OUTCSC_OFFSET:
- s->vblend_registers[offset] = value & 0x3FFF7FFF;
- break;
- case V_BLEND_CHROMA_KEY_ENABLE:
- s->vblend_registers[offset] = value & 0x00000003;
- break;
- case V_BLEND_CHROMA_KEY_COMP1:
- case V_BLEND_CHROMA_KEY_COMP2:
- case V_BLEND_CHROMA_KEY_COMP3:
- s->vblend_registers[offset] = value & 0x0FFF0FFF;
- break;
- default:
- s->vblend_registers[offset] = value;
- break;
- }
-}
-
-static uint64_t xlnx_dp_vblend_read(void *opaque, hwaddr offset,
- unsigned size)
-{
- XlnxDPState *s = XLNX_DP(opaque);
-
- DPRINTF("vblend: read @0x%" HWADDR_PRIX " = 0x%" PRIX32 "\n", offset,
- s->vblend_registers[offset >> 2]);
- return s->vblend_registers[offset >> 2];
-}
-
-static const MemoryRegionOps vblend_ops = {
- .read = xlnx_dp_vblend_read,
- .write = xlnx_dp_vblend_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
- .valid = {
- .min_access_size = 4,
- .max_access_size = 4,
- },
- .impl = {
- .min_access_size = 4,
- .max_access_size = 4,
- },
-};
-
-/*
- * This is to handle Read/Write to the Audio Video buffer manager.
- */
-static void xlnx_dp_avbufm_write(void *opaque, hwaddr offset, uint64_t value,
- unsigned size)
-{
- XlnxDPState *s = XLNX_DP(opaque);
-
- DPRINTF("avbufm: write @0x%" HWADDR_PRIX " = 0x%" PRIX32 "\n", offset,
- (uint32_t)value);
- offset = offset >> 2;
-
- switch (offset) {
- case AV_BUF_FORMAT:
- s->avbufm_registers[offset] = value & 0x00000FFF;
- xlnx_dp_change_graphic_fmt(s);
- break;
- case AV_CHBUF0:
- case AV_CHBUF1:
- case AV_CHBUF2:
- case AV_CHBUF3:
- case AV_CHBUF4:
- case AV_CHBUF5:
- s->avbufm_registers[offset] = value & 0x0000007F;
- break;
- case AV_BUF_OUTPUT_AUDIO_VIDEO_SELECT:
- s->avbufm_registers[offset] = value & 0x0000007F;
- break;
- case AV_BUF_DITHER_CONFIG:
- s->avbufm_registers[offset] = value & 0x000007FF;
- break;
- case AV_BUF_DITHER_CONFIG_MAX:
- case AV_BUF_DITHER_CONFIG_MIN:
- s->avbufm_registers[offset] = value & 0x00000FFF;
- break;
- case AV_BUF_PATTERN_GEN_SELECT:
- s->avbufm_registers[offset] = value & 0xFFFFFF03;
- break;
- case AV_BUF_AUD_VID_CLK_SOURCE:
- s->avbufm_registers[offset] = value & 0x00000007;
- break;
- case AV_BUF_SRST_REG:
- s->avbufm_registers[offset] = value & 0x00000002;
- break;
- case AV_BUF_AUDIO_CH_CONFIG:
- s->avbufm_registers[offset] = value & 0x00000003;
- break;
- case AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(0):
- case AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(1):
- case AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(2):
- case AV_BUF_VIDEO_COMP_SCALE_FACTOR(0):
- case AV_BUF_VIDEO_COMP_SCALE_FACTOR(1):
- case AV_BUF_VIDEO_COMP_SCALE_FACTOR(2):
- s->avbufm_registers[offset] = value & 0x0000FFFF;
- break;
- case AV_BUF_LIVE_VIDEO_COMP_SF(0):
- case AV_BUF_LIVE_VIDEO_COMP_SF(1):
- case AV_BUF_LIVE_VIDEO_COMP_SF(2):
- case AV_BUF_LIVE_VID_CONFIG:
- case AV_BUF_LIVE_GFX_COMP_SF(0):
- case AV_BUF_LIVE_GFX_COMP_SF(1):
- case AV_BUF_LIVE_GFX_COMP_SF(2):
- case AV_BUF_LIVE_GFX_CONFIG:
- case AV_BUF_NON_LIVE_LATENCY:
- case AV_BUF_STC_CONTROL:
- case AV_BUF_STC_INIT_VALUE0:
- case AV_BUF_STC_INIT_VALUE1:
- case AV_BUF_STC_ADJ:
- case AV_BUF_STC_VIDEO_VSYNC_TS_REG0:
- case AV_BUF_STC_VIDEO_VSYNC_TS_REG1:
- case AV_BUF_STC_EXT_VSYNC_TS_REG0:
- case AV_BUF_STC_EXT_VSYNC_TS_REG1:
- case AV_BUF_STC_CUSTOM_EVENT_TS_REG0:
- case AV_BUF_STC_CUSTOM_EVENT_TS_REG1:
- case AV_BUF_STC_CUSTOM_EVENT2_TS_REG0:
- case AV_BUF_STC_CUSTOM_EVENT2_TS_REG1:
- case AV_BUF_STC_SNAPSHOT0:
- case AV_BUF_STC_SNAPSHOT1:
- case AV_BUF_HCOUNT_VCOUNT_INT0:
- case AV_BUF_HCOUNT_VCOUNT_INT1:
- qemu_log_mask(LOG_UNIMP, "avbufm: unimplmented");
- break;
- default:
- s->avbufm_registers[offset] = value;
- break;
- }
-}
-
-static uint64_t xlnx_dp_avbufm_read(void *opaque, hwaddr offset,
- unsigned size)
-{
- XlnxDPState *s = XLNX_DP(opaque);
-
- offset = offset >> 2;
- return s->avbufm_registers[offset];
-}
-
-static const MemoryRegionOps avbufm_ops = {
- .read = xlnx_dp_avbufm_read,
- .write = xlnx_dp_avbufm_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
- .valid = {
- .min_access_size = 4,
- .max_access_size = 4,
- },
- .impl = {
- .min_access_size = 4,
- .max_access_size = 4,
- },
-};
-
-/*
- * This is a global alpha blending using pixman.
- * Both graphic and video planes are multiplied with the global alpha
- * coefficient and added.
- */
-static inline void xlnx_dp_blend_surface(XlnxDPState *s)
-{
- pixman_fixed_t alpha1[] = { pixman_double_to_fixed(1),
- pixman_double_to_fixed(1),
- pixman_double_to_fixed(1.0) };
- pixman_fixed_t alpha2[] = { pixman_double_to_fixed(1),
- pixman_double_to_fixed(1),
- pixman_double_to_fixed(1.0) };
-
- if ((surface_width(s->g_plane.surface)
- != surface_width(s->v_plane.surface)) ||
- (surface_height(s->g_plane.surface)
- != surface_height(s->v_plane.surface))) {
- return;
- }
-
- alpha1[2] = pixman_double_to_fixed((double)(xlnx_dp_global_alpha_value(s))
- / 256.0);
- alpha2[2] = pixman_double_to_fixed((255.0
- - (double)xlnx_dp_global_alpha_value(s))
- / 256.0);
-
- pixman_image_set_filter(s->g_plane.surface->image,
- PIXMAN_FILTER_CONVOLUTION, alpha1, 3);
- pixman_image_composite(PIXMAN_OP_SRC, s->g_plane.surface->image, 0,
- s->bout_plane.surface->image, 0, 0, 0, 0, 0, 0,
- surface_width(s->g_plane.surface),
- surface_height(s->g_plane.surface));
- pixman_image_set_filter(s->v_plane.surface->image,
- PIXMAN_FILTER_CONVOLUTION, alpha2, 3);
- pixman_image_composite(PIXMAN_OP_ADD, s->v_plane.surface->image, 0,
- s->bout_plane.surface->image, 0, 0, 0, 0, 0, 0,
- surface_width(s->g_plane.surface),
- surface_height(s->g_plane.surface));
-}
-
-static void xlnx_dp_update_display(void *opaque)
-{
- XlnxDPState *s = XLNX_DP(opaque);
-
- if ((s->core_registers[DP_TRANSMITTER_ENABLE] & 0x01) == 0) {
- return;
- }
-
- s->core_registers[DP_INT_STATUS] |= (1 << 13);
- xlnx_dp_update_irq(s);
-
- xlnx_dpdma_trigger_vsync_irq(s->dpdma);
-
- /*
- * Trigger the DMA channel.
- */
- if (!xlnx_dpdma_start_operation(s->dpdma, 3, false)) {
- /*
- * An error occured don't do anything with the data..
- * Trigger an underflow interrupt.
- */
- s->core_registers[DP_INT_STATUS] |= (1 << 21);
- xlnx_dp_update_irq(s);
- return;
- }
-
- if (xlnx_dp_global_alpha_enabled(s)) {
- if (!xlnx_dpdma_start_operation(s->dpdma, 0, false)) {
- s->core_registers[DP_INT_STATUS] |= (1 << 21);
- xlnx_dp_update_irq(s);
- return;
- }
- xlnx_dp_blend_surface(s);
- }
-
- /*
- * XXX: We might want to update only what changed.
- */
- dpy_gfx_update(s->console, 0, 0, surface_width(s->g_plane.surface),
- surface_height(s->g_plane.surface));
-}
-
-static const GraphicHwOps xlnx_dp_gfx_ops = {
- .gfx_update = xlnx_dp_update_display,
-};
-
-static void xlnx_dp_init(Object *obj)
-{
- SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
- XlnxDPState *s = XLNX_DP(obj);
-
- memory_region_init(&s->container, obj, TYPE_XLNX_DP, 0xC050);
-
- memory_region_init_io(&s->core_iomem, obj, &dp_ops, s, TYPE_XLNX_DP
- ".core", 0x3AF);
- memory_region_add_subregion(&s->container, 0x0000, &s->core_iomem);
-
- memory_region_init_io(&s->vblend_iomem, obj, &vblend_ops, s, TYPE_XLNX_DP
- ".v_blend", 0x1DF);
- memory_region_add_subregion(&s->container, 0xA000, &s->vblend_iomem);
-
- memory_region_init_io(&s->avbufm_iomem, obj, &avbufm_ops, s, TYPE_XLNX_DP
- ".av_buffer_manager", 0x238);
- memory_region_add_subregion(&s->container, 0xB000, &s->avbufm_iomem);
-
- memory_region_init_io(&s->audio_iomem, obj, &audio_ops, s, TYPE_XLNX_DP
- ".audio", sizeof(s->audio_registers));
- memory_region_add_subregion(&s->container, 0xC000, &s->audio_iomem);
-
- sysbus_init_mmio(sbd, &s->container);
- sysbus_init_irq(sbd, &s->irq);
-
- object_property_add_link(obj, "dpdma", TYPE_XLNX_DPDMA,
- (Object **) &s->dpdma,
- xlnx_dp_set_dpdma,
- OBJ_PROP_LINK_UNREF_ON_RELEASE,
- &error_abort);
-
- /*
- * Initialize AUX Bus.
- */
- s->aux_bus = aux_init_bus(DEVICE(obj), "aux");
-
- /*
- * Initialize DPCD and EDID..
- */
- s->dpcd = DPCD(aux_create_slave(s->aux_bus, "dpcd", 0x00000));
- s->edid = I2CDDC(qdev_create(BUS(aux_get_i2c_bus(s->aux_bus)), "i2c-ddc"));
- i2c_set_slave_address(I2C_SLAVE(s->edid), 0x50);
-
- fifo8_create(&s->rx_fifo, 16);
- fifo8_create(&s->tx_fifo, 16);
-}
-
-static void xlnx_dp_realize(DeviceState *dev, Error **errp)
-{
- XlnxDPState *s = XLNX_DP(dev);
- DisplaySurface *surface;
- struct audsettings as;
-
- s->console = graphic_console_init(dev, 0, &xlnx_dp_gfx_ops, s);
- surface = qemu_console_surface(s->console);
- xlnx_dpdma_set_host_data_location(s->dpdma, DP_GRAPHIC_DMA_CHANNEL,
- surface_data(surface));
-
- as.freq = 44100;
- as.nchannels = 2;
- as.fmt = AUD_FMT_S16;
- as.endianness = 0;
-
- AUD_register_card("xlnx_dp.audio", &s->aud_card);
-
- s->amixer_output_stream = AUD_open_out(&s->aud_card,
- s->amixer_output_stream,
- "xlnx_dp.audio.out",
- s,
- xlnx_dp_audio_callback,
- &as);
- AUD_set_volume_out(s->amixer_output_stream, 0, 255, 255);
- xlnx_dp_audio_activate(s);
-}
-
-static void xlnx_dp_reset(DeviceState *dev)
-{
- XlnxDPState *s = XLNX_DP(dev);
-
- memset(s->core_registers, 0, sizeof(s->core_registers));
- s->core_registers[DP_VERSION_REGISTER] = 0x04010000;
- s->core_registers[DP_CORE_ID] = 0x01020000;
- s->core_registers[DP_REPLY_STATUS] = 0x00000010;
- s->core_registers[DP_MSA_TRANSFER_UNIT_SIZE] = 0x00000040;
- s->core_registers[DP_INIT_WAIT] = 0x00000020;
- s->core_registers[DP_PHY_RESET] = 0x00010003;
- s->core_registers[DP_INT_MASK] = 0xFFFFF03F;
- s->core_registers[DP_PHY_STATUS] = 0x00000043;
- s->core_registers[DP_INTERRUPT_SIGNAL_STATE] = 0x00000001;
-
- s->vblend_registers[V_BLEND_RGB2YCBCR_COEFF(0)] = 0x00001000;
- s->vblend_registers[V_BLEND_RGB2YCBCR_COEFF(4)] = 0x00001000;
- s->vblend_registers[V_BLEND_RGB2YCBCR_COEFF(8)] = 0x00001000;
- s->vblend_registers[V_BLEND_IN1CSC_COEFF(0)] = 0x00001000;
- s->vblend_registers[V_BLEND_IN1CSC_COEFF(4)] = 0x00001000;
- s->vblend_registers[V_BLEND_IN1CSC_COEFF(8)] = 0x00001000;
- s->vblend_registers[V_BLEND_IN2CSC_COEFF(0)] = 0x00001000;
- s->vblend_registers[V_BLEND_IN2CSC_COEFF(4)] = 0x00001000;
- s->vblend_registers[V_BLEND_IN2CSC_COEFF(8)] = 0x00001000;
-
- s->avbufm_registers[AV_BUF_NON_LIVE_LATENCY] = 0x00000180;
- s->avbufm_registers[AV_BUF_OUTPUT_AUDIO_VIDEO_SELECT] = 0x00000008;
- s->avbufm_registers[AV_BUF_DITHER_CONFIG_MAX] = 0x00000FFF;
- s->avbufm_registers[AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(0)] = 0x00010101;
- s->avbufm_registers[AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(1)] = 0x00010101;
- s->avbufm_registers[AV_BUF_GRAPHICS_COMP_SCALE_FACTOR(2)] = 0x00010101;
- s->avbufm_registers[AV_BUF_VIDEO_COMP_SCALE_FACTOR(0)] = 0x00010101;
- s->avbufm_registers[AV_BUF_VIDEO_COMP_SCALE_FACTOR(1)] = 0x00010101;
- s->avbufm_registers[AV_BUF_VIDEO_COMP_SCALE_FACTOR(2)] = 0x00010101;
- s->avbufm_registers[AV_BUF_LIVE_VIDEO_COMP_SF(0)] = 0x00010101;
- s->avbufm_registers[AV_BUF_LIVE_VIDEO_COMP_SF(1)] = 0x00010101;
- s->avbufm_registers[AV_BUF_LIVE_VIDEO_COMP_SF(2)] = 0x00010101;
- s->avbufm_registers[AV_BUF_LIVE_GFX_COMP_SF(0)] = 0x00010101;
- s->avbufm_registers[AV_BUF_LIVE_GFX_COMP_SF(1)] = 0x00010101;
- s->avbufm_registers[AV_BUF_LIVE_GFX_COMP_SF(2)] = 0x00010101;
-
- memset(s->audio_registers, 0, sizeof(s->audio_registers));
- s->byte_left = 0;
-
- xlnx_dp_aux_clear_rx_fifo(s);
- xlnx_dp_change_graphic_fmt(s);
- xlnx_dp_update_irq(s);
-}
-
-static void xlnx_dp_class_init(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
-
- dc->realize = xlnx_dp_realize;
- dc->vmsd = &vmstate_dp;
- dc->reset = xlnx_dp_reset;
-}
-
-static const TypeInfo xlnx_dp_info = {
- .name = TYPE_XLNX_DP,
- .parent = TYPE_SYS_BUS_DEVICE,
- .instance_size = sizeof(XlnxDPState),
- .instance_init = xlnx_dp_init,
- .class_init = xlnx_dp_class_init,
-};
-
-static void xlnx_dp_register_types(void)
-{
- type_register_static(&xlnx_dp_info);
-}
-
-type_init(xlnx_dp_register_types)
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-31 11:14:25 +0000