diff options
| -rw-r--r-- | packaging/psb-headers.changes | 27 | ||||
| -rw-r--r-- | packaging/psb-headers.spec | 33 | ||||
| -rw-r--r-- | psb_drm.h | 708 | ||||
| -rw-r--r-- | psb_reg.h | 588 | ||||
| -rw-r--r-- | psb_ttm_fence_user.h | 140 | ||||
| -rw-r--r-- | psb_ttm_placement_user.h | 273 | ||||
| -rw-r--r-- | ttm_placement.h | 102 |
7 files changed, 1871 insertions, 0 deletions
diff --git a/packaging/psb-headers.changes b/packaging/psb-headers.changes new file mode 100644 index 0000000..42797f9 --- /dev/null +++ b/packaging/psb-headers.changes @@ -0,0 +1,27 @@ +* Thu Jan 19 2012 Markus Lehtonen <markus.lehtonen@linux.intel.com> 1.0.13 +- Update headers from latest medfield (v3.0) kernel + +* Mon Aug 24 2009 Prajwal Mohan <prajwal.karur.mohan@intel.com> 1.0.12 +- Update Headers + +* Wed Jul 29 2009 Prajwal Mohan <prajwal.karur.mohan@intel.com> 1.0.11 +- Update headers + +* Wed Jul 01 2009 Prajwal Mohan <prajwal.karur.mohan@intel.com> 1.0.10 +- Update headers + +* Thu Jun 18 2009 Anas Nashif <anas.nashif@intel.com> - 1.0.9 +- Update headers + +* Fri May 15 2009 Anas Nashif <anas.nashif@intel.com> 1.0.7 +- Update to latest snapshot 20090514 + +* Sun Apr 26 2009 Anas Nashif <anas.nashif@intel.com> 1.0.7 +- Update to 1.0.7 + +* Wed Apr 22 2009 Anas Nashif <anas.nashif@intel.com> 1.0.6 +- Update to 1.0.7 + +* Fri Mar 27 2009 Anas Nashif <anas.nashif@intel.com> 1.0.6 +- Initial import into moblin + diff --git a/packaging/psb-headers.spec b/packaging/psb-headers.spec new file mode 100644 index 0000000..897e2c6 --- /dev/null +++ b/packaging/psb-headers.spec @@ -0,0 +1,33 @@ +Summary: Header files for PSB Kernel module +Name: psb-headers +Version: 1.0.13 +Release: 1 +License: GPLv2 +Group: System/Kernel +BuildRoot: %{_tmppath}/%{name}-%{version}-root +Source0: %{name}-%{version}.tar.bz2 + +ExclusiveArch: %{ix86} +%description +PSB kernel module header files + +%prep +%setup -q +%build + +%install +rm -rf $RPM_BUILD_ROOT + +mkdir -p $RPM_BUILD_ROOT/usr/include/ttm +cp ttm_placement.h $RPM_BUILD_ROOT/usr/include/ttm +cp psb_reg.h psb_drm.h psb_ttm_placement_user.h psb_ttm_fence_user.h $RPM_BUILD_ROOT/usr/include + + +%clean +rm -rf $RPM_BUILD_ROOT + +%files +%defattr(-,root,root,-) +%dir %{_includedir}/ttm +%{_includedir}/ttm/*.h +%{_includedir}/*.h diff --git a/psb_drm.h b/psb_drm.h new file mode 100644 index 0000000..13f20b8 --- /dev/null +++ b/psb_drm.h @@ -0,0 +1,708 @@ +/************************************************************************** + * Copyright (c) 2007, Intel Corporation. + * All Rights Reserved. + * Copyright (c) 2008, Tungsten Graphics Inc. Cedar Park, TX., USA. + * All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * + **************************************************************************/ + +#ifndef _PSB_DRM_H_ +#define _PSB_DRM_H_ + +#if defined(__linux__) && !defined(__KERNEL__) +#include<stdint.h> +#include <linux/types.h> +#endif +#include "drm_mode.h" + +#include "psb_ttm_fence_user.h" +#include "psb_ttm_placement_user.h" + +/* + * Menlow/MRST graphics driver package version + * a.b.c.xxxx + * a - Product Family: 5 - Linux + * b - Major Release Version: 0 - non-Gallium (Unbuntu); + * 1 - Gallium (Moblin2) + * c - Hotfix Release + * xxxx - Graphics internal build # + */ +#define PSB_PACKAGE_VERSION "5.3.0.32L.0047" + +#define DRM_PSB_SAREA_MAJOR 0 +#define DRM_PSB_SAREA_MINOR 2 +#define PSB_FIXED_SHIFT 16 + +#define PSB_NUM_PIPE 3 + +/* + * Public memory types. + */ + +#define DRM_PSB_MEM_MMU TTM_PL_PRIV1 +#define DRM_PSB_FLAG_MEM_MMU TTM_PL_FLAG_PRIV1 + +#define TTM_PL_CI TTM_PL_PRIV0 +#define TTM_PL_FLAG_CI TTM_PL_FLAG_PRIV0 + +#define TTM_PL_RAR TTM_PL_PRIV2 +#define TTM_PL_FLAG_RAR TTM_PL_FLAG_PRIV2 + +typedef int32_t psb_fixed; +typedef uint32_t psb_ufixed; + +static inline int32_t psb_int_to_fixed(int a) +{ + return a * (1 << PSB_FIXED_SHIFT); +} + +static inline uint32_t psb_unsigned_to_ufixed(unsigned int a) +{ + return a << PSB_FIXED_SHIFT; +} + +/*Status of the command sent to the gfx device.*/ +typedef enum { + DRM_CMD_SUCCESS, + DRM_CMD_FAILED, + DRM_CMD_HANG +} drm_cmd_status_t; + +struct drm_psb_scanout { + uint32_t buffer_id; /* DRM buffer object ID */ + uint32_t rotation; /* Rotation as in RR_rotation definitions */ + uint32_t stride; /* Buffer stride in bytes */ + uint32_t depth; /* Buffer depth in bits (NOT) bpp */ + uint32_t width; /* Buffer width in pixels */ + uint32_t height; /* Buffer height in lines */ + int32_t transform[3][3]; /* Buffer composite transform */ + /* (scaling, rot, reflect) */ +}; + +#define DRM_PSB_SAREA_OWNERS 16 +#define DRM_PSB_SAREA_OWNER_2D 0 +#define DRM_PSB_SAREA_OWNER_3D 1 + +#define DRM_PSB_SAREA_SCANOUTS 3 + +struct drm_psb_sarea { + /* Track changes of this data structure */ + + uint32_t major; + uint32_t minor; + + /* Last context to touch part of hw */ + uint32_t ctx_owners[DRM_PSB_SAREA_OWNERS]; + + /* Definition of front- and rotated buffers */ + uint32_t num_scanouts; + struct drm_psb_scanout scanouts[DRM_PSB_SAREA_SCANOUTS]; + + int planeA_x; + int planeA_y; + int planeA_w; + int planeA_h; + int planeB_x; + int planeB_y; + int planeB_w; + int planeB_h; + /* Number of active scanouts */ + uint32_t num_active_scanouts; +}; + +#define PSB_RELOC_MAGIC 0x67676767 +#define PSB_RELOC_SHIFT_MASK 0x0000FFFF +#define PSB_RELOC_SHIFT_SHIFT 0 +#define PSB_RELOC_ALSHIFT_MASK 0xFFFF0000 +#define PSB_RELOC_ALSHIFT_SHIFT 16 + +#define PSB_RELOC_OP_OFFSET 0 /* Offset of the indicated + * buffer + */ + +struct drm_psb_reloc { + uint32_t reloc_op; + uint32_t where; /* offset in destination buffer */ + uint32_t buffer; /* Buffer reloc applies to */ + uint32_t mask; /* Destination format: */ + uint32_t shift; /* Destination format: */ + uint32_t pre_add; /* Destination format: */ + uint32_t background; /* Destination add */ + uint32_t dst_buffer; /* Destination buffer. Index into buffer_list */ + uint32_t arg0; /* Reloc-op dependant */ + uint32_t arg1; +}; + + +#define PSB_GPU_ACCESS_READ (1ULL << 32) +#define PSB_GPU_ACCESS_WRITE (1ULL << 33) +#define PSB_GPU_ACCESS_MASK (PSB_GPU_ACCESS_READ | PSB_GPU_ACCESS_WRITE) + +#define PSB_BO_FLAG_COMMAND (1ULL << 52) + +#define PSB_ENGINE_2D 0 +#define PSB_ENGINE_VIDEO 1 +#define LNC_ENGINE_ENCODE 5 + +/* + * For this fence class we have a couple of + * fence types. + */ + +#define _PSB_FENCE_EXE_SHIFT 0 +#define _PSB_FENCE_FEEDBACK_SHIFT 4 + +#define _PSB_FENCE_TYPE_EXE (1 << _PSB_FENCE_EXE_SHIFT) +#define _PSB_FENCE_TYPE_FEEDBACK (1 << _PSB_FENCE_FEEDBACK_SHIFT) + +#define PSB_NUM_ENGINES 6 + + +#define PSB_FEEDBACK_OP_VISTEST (1 << 0) + +struct drm_psb_extension_rep { + int32_t exists; + uint32_t driver_ioctl_offset; + uint32_t sarea_offset; + uint32_t major; + uint32_t minor; + uint32_t pl; +}; + +#define DRM_PSB_EXT_NAME_LEN 128 + +union drm_psb_extension_arg { + char extension[DRM_PSB_EXT_NAME_LEN]; + struct drm_psb_extension_rep rep; +}; + +struct psb_validate_req { + uint64_t set_flags; + uint64_t clear_flags; + uint64_t next; + uint64_t presumed_gpu_offset; + uint32_t buffer_handle; + uint32_t presumed_flags; + uint32_t group; + uint32_t pad64; +}; + +struct psb_validate_rep { + uint64_t gpu_offset; + uint32_t placement; + uint32_t fence_type_mask; +}; + +#define PSB_USE_PRESUMED (1 << 0) + +struct psb_validate_arg { + int handled; + int ret; + union { + struct psb_validate_req req; + struct psb_validate_rep rep; + } d; +}; + + +#define DRM_PSB_FENCE_NO_USER (1 << 0) + +struct psb_ttm_fence_rep { + uint32_t handle; + uint32_t fence_class; + uint32_t fence_type; + uint32_t signaled_types; + uint32_t error; +}; + +typedef struct drm_psb_cmdbuf_arg { + uint64_t buffer_list; /* List of buffers to validate */ + uint64_t clip_rects; /* See i915 counterpart */ + uint64_t scene_arg; + uint64_t fence_arg; + + uint32_t ta_flags; + + uint32_t ta_handle; /* TA reg-value pairs */ + uint32_t ta_offset; + uint32_t ta_size; + + uint32_t oom_handle; + uint32_t oom_offset; + uint32_t oom_size; + + uint32_t cmdbuf_handle; /* 2D Command buffer object or, */ + uint32_t cmdbuf_offset; /* rasterizer reg-value pairs */ + uint32_t cmdbuf_size; + + uint32_t reloc_handle; /* Reloc buffer object */ + uint32_t reloc_offset; + uint32_t num_relocs; + + int32_t damage; /* Damage front buffer with cliprects */ + /* Not implemented yet */ + uint32_t fence_flags; + uint32_t engine; + + /* + * Feedback; + */ + + uint32_t feedback_ops; + uint32_t feedback_handle; + uint32_t feedback_offset; + uint32_t feedback_breakpoints; + uint32_t feedback_size; +} drm_psb_cmdbuf_arg_t; + +typedef struct drm_psb_pageflip_arg { + uint32_t flip_offset; + uint32_t stride; +} drm_psb_pageflip_arg_t; + +typedef enum { + LNC_VIDEO_DEVICE_INFO, + LNC_VIDEO_GETPARAM_RAR_INFO, + LNC_VIDEO_GETPARAM_CI_INFO, + LNC_VIDEO_GETPARAM_RAR_HANDLER_OFFSET, + LNC_VIDEO_FRAME_SKIP, + IMG_VIDEO_DECODE_STATUS, + IMG_VIDEO_NEW_CONTEXT, + IMG_VIDEO_RM_CONTEXT, + IMG_VIDEO_MB_ERROR +} lnc_getparam_key_t; + +struct drm_lnc_video_getparam_arg { + lnc_getparam_key_t key; + uint64_t arg; /* argument pointer */ + uint64_t value; /* feed back pointer */ +}; + + +/* + * Feedback components: + */ + +/* + * Vistest component. The number of these in the feedback buffer + * equals the number of vistest breakpoints + 1. + * This is currently the only feedback component. + */ + +struct drm_psb_vistest { + uint32_t vt[8]; +}; + +struct drm_psb_sizes_arg { + uint32_t ta_mem_size; + uint32_t mmu_size; + uint32_t pds_size; + uint32_t rastgeom_size; + uint32_t tt_size; + uint32_t vram_size; +}; + +struct drm_psb_hist_status_arg { + uint32_t buf[32]; +}; + +struct drm_psb_dpst_lut_arg { + uint8_t lut[256]; + int output_id; +}; + +struct mrst_timing_info { + uint16_t pixel_clock; + uint8_t hactive_lo; + uint8_t hblank_lo; + uint8_t hblank_hi:4; + uint8_t hactive_hi:4; + uint8_t vactive_lo; + uint8_t vblank_lo; + uint8_t vblank_hi:4; + uint8_t vactive_hi:4; + uint8_t hsync_offset_lo; + uint8_t hsync_pulse_width_lo; + uint8_t vsync_pulse_width_lo:4; + uint8_t vsync_offset_lo:4; + uint8_t vsync_pulse_width_hi:2; + uint8_t vsync_offset_hi:2; + uint8_t hsync_pulse_width_hi:2; + uint8_t hsync_offset_hi:2; + uint8_t width_mm_lo; + uint8_t height_mm_lo; + uint8_t height_mm_hi:4; + uint8_t width_mm_hi:4; + uint8_t hborder; + uint8_t vborder; + uint8_t unknown0:1; + uint8_t hsync_positive:1; + uint8_t vsync_positive:1; + uint8_t separate_sync:2; + uint8_t stereo:1; + uint8_t unknown6:1; + uint8_t interlaced:1; +} __attribute__((packed)); + +struct gct_r10_timing_info { + uint16_t pixel_clock; + uint32_t hactive_lo:8; + uint32_t hactive_hi:4; + uint32_t hblank_lo:8; + uint32_t hblank_hi:4; + uint32_t hsync_offset_lo:8; + uint16_t hsync_offset_hi:2; + uint16_t hsync_pulse_width_lo:8; + uint16_t hsync_pulse_width_hi:2; + uint16_t hsync_positive:1; + uint16_t rsvd_1:3; + uint8_t vactive_lo:8; + uint16_t vactive_hi:4; + uint16_t vblank_lo:8; + uint16_t vblank_hi:4; + uint16_t vsync_offset_lo:4; + uint16_t vsync_offset_hi:2; + uint16_t vsync_pulse_width_lo:4; + uint16_t vsync_pulse_width_hi:2; + uint16_t vsync_positive:1; + uint16_t rsvd_2:3; +} __attribute__((packed)); + +struct mrst_panel_descriptor_v1{ + uint32_t Panel_Port_Control; /* 1 dword, Register 0x61180 if LVDS */ + /* 0x61190 if MIPI */ + uint32_t Panel_Power_On_Sequencing;/*1 dword,Register 0x61208,*/ + uint32_t Panel_Power_Off_Sequencing;/*1 dword,Register 0x6120C,*/ + uint32_t Panel_Power_Cycle_Delay_and_Reference_Divisor;/* 1 dword */ + /* Register 0x61210 */ + struct mrst_timing_info DTD;/*18 bytes, Standard definition */ + uint16_t Panel_Backlight_Inverter_Descriptor;/* 16 bits, as follows */ + /* Bit 0, Frequency, 15 bits,0 - 32767Hz */ + /* Bit 15, Polarity, 1 bit, 0: Normal, 1: Inverted */ + uint16_t Panel_MIPI_Display_Descriptor; + /*16 bits, Defined as follows: */ + /* if MIPI, 0x0000 if LVDS */ + /* Bit 0, Type, 2 bits, */ + /* 0: Type-1, */ + /* 1: Type-2, */ + /* 2: Type-3, */ + /* 3: Type-4 */ + /* Bit 2, Pixel Format, 4 bits */ + /* Bit0: 16bpp (not supported in LNC), */ + /* Bit1: 18bpp loosely packed, */ + /* Bit2: 18bpp packed, */ + /* Bit3: 24bpp */ + /* Bit 6, Reserved, 2 bits, 00b */ + /* Bit 8, Minimum Supported Frame Rate, 6 bits, 0 - 63Hz */ + /* Bit 14, Reserved, 2 bits, 00b */ +} __attribute__ ((packed)); + +struct mrst_panel_descriptor_v2{ + uint32_t Panel_Port_Control; /* 1 dword, Register 0x61180 if LVDS */ + /* 0x61190 if MIPI */ + uint32_t Panel_Power_On_Sequencing;/*1 dword,Register 0x61208,*/ + uint32_t Panel_Power_Off_Sequencing;/*1 dword,Register 0x6120C,*/ + uint8_t Panel_Power_Cycle_Delay_and_Reference_Divisor;/* 1 byte */ + /* Register 0x61210 */ + struct mrst_timing_info DTD;/*18 bytes, Standard definition */ + uint16_t Panel_Backlight_Inverter_Descriptor;/*16 bits, as follows*/ + /*Bit 0, Frequency, 16 bits, 0 - 32767Hz*/ + uint8_t Panel_Initial_Brightness;/* [7:0] 0 - 100% */ + /*Bit 7, Polarity, 1 bit,0: Normal, 1: Inverted*/ + uint16_t Panel_MIPI_Display_Descriptor; + /*16 bits, Defined as follows: */ + /* if MIPI, 0x0000 if LVDS */ + /* Bit 0, Type, 2 bits, */ + /* 0: Type-1, */ + /* 1: Type-2, */ + /* 2: Type-3, */ + /* 3: Type-4 */ + /* Bit 2, Pixel Format, 4 bits */ + /* Bit0: 16bpp (not supported in LNC), */ + /* Bit1: 18bpp loosely packed, */ + /* Bit2: 18bpp packed, */ + /* Bit3: 24bpp */ + /* Bit 6, Reserved, 2 bits, 00b */ + /* Bit 8, Minimum Supported Frame Rate, 6 bits, 0 - 63Hz */ + /* Bit 14, Reserved, 2 bits, 00b */ +} __attribute__ ((packed)); + +union mrst_panel_rx{ + struct{ + uint16_t NumberOfLanes:2; /*Num of Lanes, 2 bits,0 = 1 lane,*/ + /* 1 = 2 lanes, 2 = 3 lanes, 3 = 4 lanes. */ + uint16_t MaxLaneFreq:3; /* 0: 100MHz, 1: 200MHz, 2: 300MHz, */ + /*3: 400MHz, 4: 500MHz, 5: 600MHz, 6: 700MHz, 7: 800MHz.*/ + uint16_t SupportedVideoTransferMode:2; /*0: Non-burst only */ + /* 1: Burst and non-burst */ + /* 2/3: Reserved */ + uint16_t HSClkBehavior:1; /*0: Continuous, 1: Non-continuous*/ + uint16_t DuoDisplaySupport:1; /*1 bit,0: No, 1: Yes*/ + uint16_t ECC_ChecksumCapabilities:1;/*1 bit,0: No, 1: Yes*/ + uint16_t BidirectionalCommunication:1;/*1 bit,0: No, 1: Yes */ + uint16_t Rsvd:5;/*5 bits,00000b */ + } panelrx; + uint16_t panel_receiver; +} __attribute__ ((packed)); + +struct gct_ioctl_arg{ + uint8_t bpi; /* boot panel index, number of panel used during boot */ + uint8_t pt; /* panel type, 4 bit field, 0=lvds, 1=mipi */ + struct mrst_timing_info DTD; /* timing info for the selected panel */ + uint32_t Panel_Port_Control; + uint32_t PP_On_Sequencing;/*1 dword,Register 0x61208,*/ + uint32_t PP_Off_Sequencing;/*1 dword,Register 0x6120C,*/ + uint32_t PP_Cycle_Delay; + uint16_t Panel_Backlight_Inverter_Descriptor; + uint16_t Panel_MIPI_Display_Descriptor; +} __attribute__ ((packed)); + +struct mrst_vbt{ + char Signature[4]; /*4 bytes,"$GCT" */ + uint8_t Revision; /*1 byte */ + uint8_t Size; /*1 byte */ + uint8_t Checksum; /*1 byte,Calculated*/ + void *mrst_gct; +} __attribute__ ((packed)); + +struct mrst_gct_v1{ /* expect this table to change per customer request*/ + union{ /*8 bits,Defined as follows: */ + struct{ + uint8_t PanelType:4; /*4 bits, Bit field for panels*/ + /* 0 - 3: 0 = LVDS, 1 = MIPI*/ + /*2 bits,Specifies which of the*/ + uint8_t BootPanelIndex:2; + /* 4 panels to use by default*/ + uint8_t BootMIPI_DSI_RxIndex:2;/*Specifies which of*/ + /* the 4 MIPI DSI receivers to use*/ + } PD; + uint8_t PanelDescriptor; + }; + struct mrst_panel_descriptor_v1 panel[4];/*panel descrs,38 bytes each*/ + union mrst_panel_rx panelrx[4]; /* panel receivers*/ +} __attribute__ ((packed)); + +struct mrst_gct_v2{ /* expect this table to change per customer request*/ + union{ /*8 bits,Defined as follows: */ + struct{ + uint8_t PanelType:4; /*4 bits, Bit field for panels*/ + /* 0 - 3: 0 = LVDS, 1 = MIPI*/ + /*2 bits,Specifies which of the*/ + uint8_t BootPanelIndex:2; + /* 4 panels to use by default*/ + uint8_t BootMIPI_DSI_RxIndex:2;/*Specifies which of*/ + /* the 4 MIPI DSI receivers to use*/ + } PD; + uint8_t PanelDescriptor; + }; + struct mrst_panel_descriptor_v2 panel[4];/*panel descrs,38 bytes each*/ + union mrst_panel_rx panelrx[4]; /* panel receivers*/ +} __attribute__ ((packed)); + +#define PSB_DC_CRTC_SAVE 0x01 +#define PSB_DC_CRTC_RESTORE 0x02 +#define PSB_DC_OUTPUT_SAVE 0x04 +#define PSB_DC_OUTPUT_RESTORE 0x08 +#define PSB_DC_CRTC_MASK 0x03 +#define PSB_DC_OUTPUT_MASK 0x0C + +struct drm_psb_dc_state_arg { + uint32_t flags; + uint32_t obj_id; +}; + +struct drm_psb_mode_operation_arg { + uint32_t obj_id; + uint16_t operation; + struct drm_mode_modeinfo mode; + void *data; +}; + +struct drm_psb_stolen_memory_arg { + uint32_t base; + uint32_t size; +}; + +/*Display Register Bits*/ +#define REGRWBITS_PFIT_CONTROLS (1 << 0) +#define REGRWBITS_PFIT_AUTOSCALE_RATIOS (1 << 1) +#define REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS (1 << 2) +#define REGRWBITS_PIPEASRC (1 << 3) +#define REGRWBITS_PIPEBSRC (1 << 4) +#define REGRWBITS_VTOTAL_A (1 << 5) +#define REGRWBITS_VTOTAL_B (1 << 6) +#define REGRWBITS_DSPACNTR (1 << 8) +#define REGRWBITS_DSPBCNTR (1 << 9) +#define REGRWBITS_DSPCCNTR (1 << 10) + +/*Overlay Register Bits*/ +#define OV_REGRWBITS_OVADD (1 << 0) +#define OV_REGRWBITS_OGAM_ALL (1 << 1) + +#define OVC_REGRWBITS_OVADD (1 << 2) +#define OVC_REGRWBITS_OGAM_ALL (1 << 3) + +struct drm_psb_register_rw_arg { + uint32_t b_force_hw_on; + + uint32_t display_read_mask; + uint32_t display_write_mask; + + struct { + uint32_t pfit_controls; + uint32_t pfit_autoscale_ratios; + uint32_t pfit_programmed_scale_ratios; + uint32_t pipeasrc; + uint32_t pipebsrc; + uint32_t vtotal_a; + uint32_t vtotal_b; + uint32_t dspcntr_a; + uint32_t dspcntr_b; + } display; + + uint32_t overlay_read_mask; + uint32_t overlay_write_mask; + + struct { + uint32_t OVADD; + uint32_t OGAMC0; + uint32_t OGAMC1; + uint32_t OGAMC2; + uint32_t OGAMC3; + uint32_t OGAMC4; + uint32_t OGAMC5; + uint32_t IEP_ENABLED; + uint32_t IEP_BLE_MINMAX; + uint32_t IEP_BSSCC_CONTROL; + uint32_t b_wait_vblank; + } overlay; + + uint32_t sprite_enable_mask; + uint32_t sprite_disable_mask; + + struct { + uint32_t dspa_control; + uint32_t dspa_key_value; + uint32_t dspa_key_mask; + uint32_t dspc_control; + uint32_t dspc_stride; + uint32_t dspc_position; + uint32_t dspc_linear_offset; + uint32_t dspc_size; + uint32_t dspc_surface; + } sprite; + + uint32_t subpicture_enable_mask; + uint32_t subpicture_disable_mask; +}; + +struct psb_gtt_mapping_arg { + void *hKernelMemInfo; + uint32_t offset_pages; +}; + +struct drm_psb_getpageaddrs_arg { + uint32_t handle; + unsigned long *page_addrs; + unsigned long gtt_offset; +}; + + +#define MAX_SLICES_PER_PICTURE 72 +typedef struct drm_psb_msvdx_decode_status { + uint32_t fw_status; + uint32_t num_error_slice; + int32_t start_error_mb_list[MAX_SLICES_PER_PICTURE]; + int32_t end_error_mb_list[MAX_SLICES_PER_PICTURE]; + int32_t slice_missing_or_error[MAX_SLICES_PER_PICTURE]; +} drm_psb_msvdx_decode_status_t; + +/* Controlling the kernel modesetting buffers */ + +#define DRM_PSB_KMS_OFF 0x00 +#define DRM_PSB_KMS_ON 0x01 +#define DRM_PSB_VT_LEAVE 0x02 +#define DRM_PSB_VT_ENTER 0x03 +#define DRM_PSB_EXTENSION 0x06 +#define DRM_PSB_SIZES 0x07 +#define DRM_PSB_FUSE_REG 0x08 +#define DRM_PSB_VBT 0x09 +#define DRM_PSB_DC_STATE 0x0A +#define DRM_PSB_ADB 0x0B +#define DRM_PSB_MODE_OPERATION 0x0C +#define DRM_PSB_STOLEN_MEMORY 0x0D +#define DRM_PSB_REGISTER_RW 0x0E +#define DRM_PSB_GTT_MAP 0x0F +#define DRM_PSB_GTT_UNMAP 0x10 +#define DRM_PSB_GETPAGEADDRS 0x11 +/** + * NOTE: Add new commands here, but increment + * the values below and increment their + * corresponding defines where they're + * defined elsewhere. + */ +#define DRM_PVR_RESERVED1 0x12 +#define DRM_PVR_RESERVED2 0x13 +#define DRM_PVR_RESERVED3 0x14 +#define DRM_PVR_RESERVED4 0x15 +#define DRM_PVR_RESERVED5 0x16 + +#define DRM_PSB_HIST_ENABLE 0x17 +#define DRM_PSB_HIST_STATUS 0x18 +#define DRM_PSB_UPDATE_GUARD 0x19 +#define DRM_PSB_INIT_COMM 0x1A +#define DRM_PSB_DPST 0x1B +#define DRM_PSB_GAMMA 0x1C +#define DRM_PSB_DPST_BL 0x1D + +#define DRM_PVR_RESERVED6 0x1E + +#define DRM_PSB_GET_PIPE_FROM_CRTC_ID 0x1F +#define DRM_PSB_DPU_QUERY 0x20 +#define DRM_PSB_DPU_DSR_ON 0x21 +#define DRM_PSB_DPU_DSR_OFF 0x22 + +#define DRM_PSB_DSR_ENABLE 0xfffffffe +#define DRM_PSB_DSR_DISABLE 0xffffffff + +struct psb_drm_dpu_rect { + int x, y; + int width, height; +}; + +struct drm_psb_drv_dsr_off_arg { + int screen; + struct psb_drm_dpu_rect damage_rect; +}; + + +struct drm_psb_dev_info_arg { + uint32_t num_use_attribute_registers; +}; +#define DRM_PSB_DEVINFO 0x01 + +#define PSB_MODE_OPERATION_MODE_VALID 0x01 +#define PSB_MODE_OPERATION_SET_DC_BASE 0x02 + +struct drm_psb_get_pipe_from_crtc_id_arg { + /** ID of CRTC being requested **/ + uint32_t crtc_id; + + /** pipe of requested CRTC **/ + uint32_t pipe; +}; + +#endif diff --git a/psb_reg.h b/psb_reg.h new file mode 100644 index 0000000..89a05fa --- /dev/null +++ b/psb_reg.h @@ -0,0 +1,588 @@ +/************************************************************************** + * + * Copyright (c) (2005-2007) Imagination Technologies Limited. + * Copyright (c) 2007, Intel Corporation. + * All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.. + * + **************************************************************************/ + +#ifndef _PSB_REG_H_ +#define _PSB_REG_H_ + +#define PSB_CR_CLKGATECTL 0x0000 +#define _PSB_C_CLKGATECTL_AUTO_MAN_REG (1 << 24) +#define _PSB_C_CLKGATECTL_USE_CLKG_SHIFT (20) +#define _PSB_C_CLKGATECTL_USE_CLKG_MASK (0x3 << 20) +#define _PSB_C_CLKGATECTL_DPM_CLKG_SHIFT (16) +#define _PSB_C_CLKGATECTL_DPM_CLKG_MASK (0x3 << 16) +#define _PSB_C_CLKGATECTL_TA_CLKG_SHIFT (12) +#define _PSB_C_CLKGATECTL_TA_CLKG_MASK (0x3 << 12) +#define _PSB_C_CLKGATECTL_TSP_CLKG_SHIFT (8) +#define _PSB_C_CLKGATECTL_TSP_CLKG_MASK (0x3 << 8) +#define _PSB_C_CLKGATECTL_ISP_CLKG_SHIFT (4) +#define _PSB_C_CLKGATECTL_ISP_CLKG_MASK (0x3 << 4) +#define _PSB_C_CLKGATECTL_2D_CLKG_SHIFT (0) +#define _PSB_C_CLKGATECTL_2D_CLKG_MASK (0x3 << 0) +#define _PSB_C_CLKGATECTL_CLKG_ENABLED (0) +#define _PSB_C_CLKGATECTL_CLKG_DISABLED (1) +#define _PSB_C_CLKGATECTL_CLKG_AUTO (2) + +#define PSB_CR_CORE_ID 0x0010 +#define _PSB_CC_ID_ID_SHIFT (16) +#define _PSB_CC_ID_ID_MASK (0xFFFF << 16) +#define _PSB_CC_ID_CONFIG_SHIFT (0) +#define _PSB_CC_ID_CONFIG_MASK (0xFFFF << 0) + +#define PSB_CR_CORE_REVISION 0x0014 +#define _PSB_CC_REVISION_DESIGNER_SHIFT (24) +#define _PSB_CC_REVISION_DESIGNER_MASK (0xFF << 24) +#define _PSB_CC_REVISION_MAJOR_SHIFT (16) +#define _PSB_CC_REVISION_MAJOR_MASK (0xFF << 16) +#define _PSB_CC_REVISION_MINOR_SHIFT (8) +#define _PSB_CC_REVISION_MINOR_MASK (0xFF << 8) +#define _PSB_CC_REVISION_MAINTENANCE_SHIFT (0) +#define _PSB_CC_REVISION_MAINTENANCE_MASK (0xFF << 0) + +#define PSB_CR_DESIGNER_REV_FIELD1 0x0018 + +#define PSB_CR_SOFT_RESET 0x0080 +#define _PSB_CS_RESET_TSP_RESET (1 << 6) +#define _PSB_CS_RESET_ISP_RESET (1 << 5) +#define _PSB_CS_RESET_USE_RESET (1 << 4) +#define _PSB_CS_RESET_TA_RESET (1 << 3) +#define _PSB_CS_RESET_DPM_RESET (1 << 2) +#define _PSB_CS_RESET_TWOD_RESET (1 << 1) +#define _PSB_CS_RESET_BIF_RESET (1 << 0) + +#define PSB_CR_DESIGNER_REV_FIELD2 0x001C + +#define PSB_CR_EVENT_HOST_ENABLE2 0x0110 + +#define PSB_CR_EVENT_STATUS2 0x0118 + +#define PSB_CR_EVENT_HOST_CLEAR2 0x0114 +#define _PSB_CE2_BIF_REQUESTER_FAULT (1 << 4) + +#define PSB_CR_EVENT_STATUS 0x012C + +#define PSB_CR_EVENT_HOST_ENABLE 0x0130 + +#define PSB_CR_EVENT_HOST_CLEAR 0x0134 +#define _PSB_CE_MASTER_INTERRUPT (1 << 31) +#define _PSB_CE_TA_DPM_FAULT (1 << 28) +#define _PSB_CE_TWOD_COMPLETE (1 << 27) +#define _PSB_CE_DPM_OUT_OF_MEMORY_ZLS (1 << 25) +#define _PSB_CE_DPM_TA_MEM_FREE (1 << 24) +#define _PSB_CE_PIXELBE_END_RENDER (1 << 18) +#define _PSB_CE_SW_EVENT (1 << 14) +#define _PSB_CE_TA_FINISHED (1 << 13) +#define _PSB_CE_TA_TERMINATE (1 << 12) +#define _PSB_CE_DPM_REACHED_MEM_THRESH (1 << 3) +#define _PSB_CE_DPM_OUT_OF_MEMORY_GBL (1 << 2) +#define _PSB_CE_DPM_OUT_OF_MEMORY_MT (1 << 1) +#define _PSB_CE_DPM_3D_MEM_FREE (1 << 0) + + +#define PSB_USE_OFFSET_MASK 0x0007FFFF +#define PSB_USE_OFFSET_SIZE (PSB_USE_OFFSET_MASK + 1) +#define PSB_CR_USE_CODE_BASE0 0x0A0C +#define PSB_CR_USE_CODE_BASE1 0x0A10 +#define PSB_CR_USE_CODE_BASE2 0x0A14 +#define PSB_CR_USE_CODE_BASE3 0x0A18 +#define PSB_CR_USE_CODE_BASE4 0x0A1C +#define PSB_CR_USE_CODE_BASE5 0x0A20 +#define PSB_CR_USE_CODE_BASE6 0x0A24 +#define PSB_CR_USE_CODE_BASE7 0x0A28 +#define PSB_CR_USE_CODE_BASE8 0x0A2C +#define PSB_CR_USE_CODE_BASE9 0x0A30 +#define PSB_CR_USE_CODE_BASE10 0x0A34 +#define PSB_CR_USE_CODE_BASE11 0x0A38 +#define PSB_CR_USE_CODE_BASE12 0x0A3C +#define PSB_CR_USE_CODE_BASE13 0x0A40 +#define PSB_CR_USE_CODE_BASE14 0x0A44 +#define PSB_CR_USE_CODE_BASE15 0x0A48 +#define PSB_CR_USE_CODE_BASE(_i) (0x0A0C + ((_i) << 2)) +#define _PSB_CUC_BASE_DM_SHIFT (25) +#define _PSB_CUC_BASE_DM_MASK (0x3 << 25) +#define _PSB_CUC_BASE_ADDR_SHIFT (0) /* 1024-bit aligned address? */ +#define _PSB_CUC_BASE_ADDR_ALIGNSHIFT (7) +#define _PSB_CUC_BASE_ADDR_MASK (0x1FFFFFF << 0) +#define _PSB_CUC_DM_VERTEX (0) +#define _PSB_CUC_DM_PIXEL (1) +#define _PSB_CUC_DM_RESERVED (2) +#define _PSB_CUC_DM_EDM (3) + +#define PSB_CR_PDS_EXEC_BASE 0x0AB8 +#define _PSB_CR_PDS_EXEC_BASE_ADDR_SHIFT (20) /* 1MB aligned address */ +#define _PSB_CR_PDS_EXEC_BASE_ADDR_ALIGNSHIFT (20) + +#define PSB_CR_EVENT_KICKER 0x0AC4 +#define _PSB_CE_KICKER_ADDRESS_SHIFT (4) /* 128-bit aligned address */ + +#define PSB_CR_EVENT_KICK 0x0AC8 +#define _PSB_CE_KICK_NOW (1 << 0) + + +#define PSB_CR_BIF_DIR_LIST_BASE1 0x0C38 + +#define PSB_CR_BIF_CTRL 0x0C00 +#define _PSB_CB_CTRL_CLEAR_FAULT (1 << 4) +#define _PSB_CB_CTRL_INVALDC (1 << 3) +#define _PSB_CB_CTRL_FLUSH (1 << 2) + +#define PSB_CR_BIF_INT_STAT 0x0C04 + +#define PSB_CR_BIF_FAULT 0x0C08 +#define _PSB_CBI_STAT_PF_N_RW (1 << 14) +#define _PSB_CBI_STAT_FAULT_SHIFT (0) +#define _PSB_CBI_STAT_FAULT_MASK (0x3FFF << 0) +#define _PSB_CBI_STAT_FAULT_CACHE (1 << 1) +#define _PSB_CBI_STAT_FAULT_TA (1 << 2) +#define _PSB_CBI_STAT_FAULT_VDM (1 << 3) +#define _PSB_CBI_STAT_FAULT_2D (1 << 4) +#define _PSB_CBI_STAT_FAULT_PBE (1 << 5) +#define _PSB_CBI_STAT_FAULT_TSP (1 << 6) +#define _PSB_CBI_STAT_FAULT_ISP (1 << 7) +#define _PSB_CBI_STAT_FAULT_USSEPDS (1 << 8) +#define _PSB_CBI_STAT_FAULT_HOST (1 << 9) + +#define PSB_CR_BIF_BANK0 0x0C78 + +#define PSB_CR_BIF_BANK1 0x0C7C + +#define PSB_CR_BIF_DIR_LIST_BASE0 0x0C84 + +#define PSB_CR_BIF_TWOD_REQ_BASE 0x0C88 +#define PSB_CR_BIF_3D_REQ_BASE 0x0CAC + +#define PSB_CR_2D_SOCIF 0x0E18 +#define _PSB_C2_SOCIF_FREESPACE_SHIFT (0) +#define _PSB_C2_SOCIF_FREESPACE_MASK (0xFF << 0) +#define _PSB_C2_SOCIF_EMPTY (0x80 << 0) + +#define PSB_CR_2D_BLIT_STATUS 0x0E04 +#define _PSB_C2B_STATUS_BUSY (1 << 24) +#define _PSB_C2B_STATUS_COMPLETE_SHIFT (0) +#define _PSB_C2B_STATUS_COMPLETE_MASK (0xFFFFFF << 0) + +/* + * 2D defs. + */ + +/* + * 2D Slave Port Data : Block Header's Object Type + */ + +#define PSB_2D_CLIP_BH (0x00000000) +#define PSB_2D_PAT_BH (0x10000000) +#define PSB_2D_CTRL_BH (0x20000000) +#define PSB_2D_SRC_OFF_BH (0x30000000) +#define PSB_2D_MASK_OFF_BH (0x40000000) +#define PSB_2D_RESERVED1_BH (0x50000000) +#define PSB_2D_RESERVED2_BH (0x60000000) +#define PSB_2D_FENCE_BH (0x70000000) +#define PSB_2D_BLIT_BH (0x80000000) +#define PSB_2D_SRC_SURF_BH (0x90000000) +#define PSB_2D_DST_SURF_BH (0xA0000000) +#define PSB_2D_PAT_SURF_BH (0xB0000000) +#define PSB_2D_SRC_PAL_BH (0xC0000000) +#define PSB_2D_PAT_PAL_BH (0xD0000000) +#define PSB_2D_MASK_SURF_BH (0xE0000000) +#define PSB_2D_FLUSH_BH (0xF0000000) + +/* + * Clip Definition block (PSB_2D_CLIP_BH) + */ +#define PSB_2D_CLIPCOUNT_MAX (1) +#define PSB_2D_CLIPCOUNT_MASK (0x00000000) +#define PSB_2D_CLIPCOUNT_CLRMASK (0xFFFFFFFF) +#define PSB_2D_CLIPCOUNT_SHIFT (0) +/* clip rectangle min & max */ +#define PSB_2D_CLIP_XMAX_MASK (0x00FFF000) +#define PSB_2D_CLIP_XMAX_CLRMASK (0xFF000FFF) +#define PSB_2D_CLIP_XMAX_SHIFT (12) +#define PSB_2D_CLIP_XMIN_MASK (0x00000FFF) +#define PSB_2D_CLIP_XMIN_CLRMASK (0x00FFF000) +#define PSB_2D_CLIP_XMIN_SHIFT (0) +/* clip rectangle offset */ +#define PSB_2D_CLIP_YMAX_MASK (0x00FFF000) +#define PSB_2D_CLIP_YMAX_CLRMASK (0xFF000FFF) +#define PSB_2D_CLIP_YMAX_SHIFT (12) +#define PSB_2D_CLIP_YMIN_MASK (0x00000FFF) +#define PSB_2D_CLIP_YMIN_CLRMASK (0x00FFF000) +#define PSB_2D_CLIP_YMIN_SHIFT (0) + +/* + * Pattern Control (PSB_2D_PAT_BH) + */ +#define PSB_2D_PAT_HEIGHT_MASK (0x0000001F) +#define PSB_2D_PAT_HEIGHT_SHIFT (0) +#define PSB_2D_PAT_WIDTH_MASK (0x000003E0) +#define PSB_2D_PAT_WIDTH_SHIFT (5) +#define PSB_2D_PAT_YSTART_MASK (0x00007C00) +#define PSB_2D_PAT_YSTART_SHIFT (10) +#define PSB_2D_PAT_XSTART_MASK (0x000F8000) +#define PSB_2D_PAT_XSTART_SHIFT (15) + +/* + * 2D Control block (PSB_2D_CTRL_BH) + */ +/* Present Flags */ +#define PSB_2D_SRCCK_CTRL (0x00000001) +#define PSB_2D_DSTCK_CTRL (0x00000002) +#define PSB_2D_ALPHA_CTRL (0x00000004) +/* Colour Key Colour (SRC/DST)*/ +#define PSB_2D_CK_COL_MASK (0xFFFFFFFF) +#define PSB_2D_CK_COL_CLRMASK (0x00000000) +#define PSB_2D_CK_COL_SHIFT (0) +/* Colour Key Mask (SRC/DST)*/ +#define PSB_2D_CK_MASK_MASK (0xFFFFFFFF) +#define PSB_2D_CK_MASK_CLRMASK (0x00000000) +#define PSB_2D_CK_MASK_SHIFT (0) +/* Alpha Control (Alpha/RGB)*/ +#define PSB_2D_GBLALPHA_MASK (0x000FF000) +#define PSB_2D_GBLALPHA_CLRMASK (0xFFF00FFF) +#define PSB_2D_GBLALPHA_SHIFT (12) +#define PSB_2D_SRCALPHA_OP_MASK (0x00700000) +#define PSB_2D_SRCALPHA_OP_CLRMASK (0xFF8FFFFF) +#define PSB_2D_SRCALPHA_OP_SHIFT (20) +#define PSB_2D_SRCALPHA_OP_ONE (0x00000000) +#define PSB_2D_SRCALPHA_OP_SRC (0x00100000) +#define PSB_2D_SRCALPHA_OP_DST (0x00200000) +#define PSB_2D_SRCALPHA_OP_SG (0x00300000) +#define PSB_2D_SRCALPHA_OP_DG (0x00400000) +#define PSB_2D_SRCALPHA_OP_GBL (0x00500000) +#define PSB_2D_SRCALPHA_OP_ZERO (0x00600000) +#define PSB_2D_SRCALPHA_INVERT (0x00800000) +#define PSB_2D_SRCALPHA_INVERT_CLR (0xFF7FFFFF) +#define PSB_2D_DSTALPHA_OP_MASK (0x07000000) +#define PSB_2D_DSTALPHA_OP_CLRMASK (0xF8FFFFFF) +#define PSB_2D_DSTALPHA_OP_SHIFT (24) +#define PSB_2D_DSTALPHA_OP_ONE (0x00000000) +#define PSB_2D_DSTALPHA_OP_SRC (0x01000000) +#define PSB_2D_DSTALPHA_OP_DST (0x02000000) +#define PSB_2D_DSTALPHA_OP_SG (0x03000000) +#define PSB_2D_DSTALPHA_OP_DG (0x04000000) +#define PSB_2D_DSTALPHA_OP_GBL (0x05000000) +#define PSB_2D_DSTALPHA_OP_ZERO (0x06000000) +#define PSB_2D_DSTALPHA_INVERT (0x08000000) +#define PSB_2D_DSTALPHA_INVERT_CLR (0xF7FFFFFF) + +#define PSB_2D_PRE_MULTIPLICATION_ENABLE (0x10000000) +#define PSB_2D_PRE_MULTIPLICATION_CLRMASK (0xEFFFFFFF) +#define PSB_2D_ZERO_SOURCE_ALPHA_ENABLE (0x20000000) +#define PSB_2D_ZERO_SOURCE_ALPHA_CLRMASK (0xDFFFFFFF) + +/* + *Source Offset (PSB_2D_SRC_OFF_BH) + */ +#define PSB_2D_SRCOFF_XSTART_MASK ((0x00000FFF) << 12) +#define PSB_2D_SRCOFF_XSTART_SHIFT (12) +#define PSB_2D_SRCOFF_YSTART_MASK (0x00000FFF) +#define PSB_2D_SRCOFF_YSTART_SHIFT (0) + +/* + * Mask Offset (PSB_2D_MASK_OFF_BH) + */ +#define PSB_2D_MASKOFF_XSTART_MASK ((0x00000FFF) << 12) +#define PSB_2D_MASKOFF_XSTART_SHIFT (12) +#define PSB_2D_MASKOFF_YSTART_MASK (0x00000FFF) +#define PSB_2D_MASKOFF_YSTART_SHIFT (0) + +/* + * 2D Fence (see PSB_2D_FENCE_BH): bits 0:27 are ignored + */ + +/* + *Blit Rectangle (PSB_2D_BLIT_BH) + */ + +#define PSB_2D_ROT_MASK (3<<25) +#define PSB_2D_ROT_CLRMASK (~PSB_2D_ROT_MASK) +#define PSB_2D_ROT_NONE (0<<25) +#define PSB_2D_ROT_90DEGS (1<<25) +#define PSB_2D_ROT_180DEGS (2<<25) +#define PSB_2D_ROT_270DEGS (3<<25) + +#define PSB_2D_COPYORDER_MASK (3<<23) +#define PSB_2D_COPYORDER_CLRMASK (~PSB_2D_COPYORDER_MASK) +#define PSB_2D_COPYORDER_TL2BR (0<<23) +#define PSB_2D_COPYORDER_BR2TL (1<<23) +#define PSB_2D_COPYORDER_TR2BL (2<<23) +#define PSB_2D_COPYORDER_BL2TR (3<<23) + +#define PSB_2D_DSTCK_CLRMASK (0xFF9FFFFF) +#define PSB_2D_DSTCK_DISABLE (0x00000000) +#define PSB_2D_DSTCK_PASS (0x00200000) +#define PSB_2D_DSTCK_REJECT (0x00400000) + +#define PSB_2D_SRCCK_CLRMASK (0xFFE7FFFF) +#define PSB_2D_SRCCK_DISABLE (0x00000000) +#define PSB_2D_SRCCK_PASS (0x00080000) +#define PSB_2D_SRCCK_REJECT (0x00100000) + +#define PSB_2D_CLIP_ENABLE (0x00040000) + +#define PSB_2D_ALPHA_ENABLE (0x00020000) + +#define PSB_2D_PAT_CLRMASK (0xFFFEFFFF) +#define PSB_2D_PAT_MASK (0x00010000) +#define PSB_2D_USE_PAT (0x00010000) +#define PSB_2D_USE_FILL (0x00000000) +/* + * Tungsten Graphics note on rop codes: If rop A and rop B are + * identical, the mask surface will not be read and need not be + * set up. + */ + +#define PSB_2D_ROP3B_MASK (0x0000FF00) +#define PSB_2D_ROP3B_CLRMASK (0xFFFF00FF) +#define PSB_2D_ROP3B_SHIFT (8) +/* rop code A */ +#define PSB_2D_ROP3A_MASK (0x000000FF) +#define PSB_2D_ROP3A_CLRMASK (0xFFFFFF00) +#define PSB_2D_ROP3A_SHIFT (0) + +#define PSB_2D_ROP4_MASK (0x0000FFFF) +/* + * DWORD0: (Only pass if Pattern control == Use Fill Colour) + * Fill Colour RGBA8888 + */ +#define PSB_2D_FILLCOLOUR_MASK (0xFFFFFFFF) +#define PSB_2D_FILLCOLOUR_SHIFT (0) +/* + * DWORD1: (Always Present) + * X Start (Dest) + * Y Start (Dest) + */ +#define PSB_2D_DST_XSTART_MASK (0x00FFF000) +#define PSB_2D_DST_XSTART_CLRMASK (0xFF000FFF) +#define PSB_2D_DST_XSTART_SHIFT (12) +#define PSB_2D_DST_YSTART_MASK (0x00000FFF) +#define PSB_2D_DST_YSTART_CLRMASK (0xFFFFF000) +#define PSB_2D_DST_YSTART_SHIFT (0) +/* + * DWORD2: (Always Present) + * X Size (Dest) + * Y Size (Dest) + */ +#define PSB_2D_DST_XSIZE_MASK (0x00FFF000) +#define PSB_2D_DST_XSIZE_CLRMASK (0xFF000FFF) +#define PSB_2D_DST_XSIZE_SHIFT (12) +#define PSB_2D_DST_YSIZE_MASK (0x00000FFF) +#define PSB_2D_DST_YSIZE_CLRMASK (0xFFFFF000) +#define PSB_2D_DST_YSIZE_SHIFT (0) + +/* + * Source Surface (PSB_2D_SRC_SURF_BH) + */ +/* + * WORD 0 + */ + +#define PSB_2D_SRC_FORMAT_MASK (0x00078000) +#define PSB_2D_SRC_1_PAL (0x00000000) +#define PSB_2D_SRC_2_PAL (0x00008000) +#define PSB_2D_SRC_4_PAL (0x00010000) +#define PSB_2D_SRC_8_PAL (0x00018000) +#define PSB_2D_SRC_8_ALPHA (0x00020000) +#define PSB_2D_SRC_4_ALPHA (0x00028000) +#define PSB_2D_SRC_332RGB (0x00030000) +#define PSB_2D_SRC_4444ARGB (0x00038000) +#define PSB_2D_SRC_555RGB (0x00040000) +#define PSB_2D_SRC_1555ARGB (0x00048000) +#define PSB_2D_SRC_565RGB (0x00050000) +#define PSB_2D_SRC_0888ARGB (0x00058000) +#define PSB_2D_SRC_8888ARGB (0x00060000) +#define PSB_2D_SRC_8888UYVY (0x00068000) +#define PSB_2D_SRC_RESERVED (0x00070000) +#define PSB_2D_SRC_1555ARGB_LOOKUP (0x00078000) + + +#define PSB_2D_SRC_STRIDE_MASK (0x00007FFF) +#define PSB_2D_SRC_STRIDE_CLRMASK (0xFFFF8000) +#define PSB_2D_SRC_STRIDE_SHIFT (0) +/* + * WORD 1 - Base Address + */ +#define PSB_2D_SRC_ADDR_MASK (0x0FFFFFFC) +#define PSB_2D_SRC_ADDR_CLRMASK (0x00000003) +#define PSB_2D_SRC_ADDR_SHIFT (2) +#define PSB_2D_SRC_ADDR_ALIGNSHIFT (2) + +/* + * Pattern Surface (PSB_2D_PAT_SURF_BH) + */ +/* + * WORD 0 + */ + +#define PSB_2D_PAT_FORMAT_MASK (0x00078000) +#define PSB_2D_PAT_1_PAL (0x00000000) +#define PSB_2D_PAT_2_PAL (0x00008000) +#define PSB_2D_PAT_4_PAL (0x00010000) +#define PSB_2D_PAT_8_PAL (0x00018000) +#define PSB_2D_PAT_8_ALPHA (0x00020000) +#define PSB_2D_PAT_4_ALPHA (0x00028000) +#define PSB_2D_PAT_332RGB (0x00030000) +#define PSB_2D_PAT_4444ARGB (0x00038000) +#define PSB_2D_PAT_555RGB (0x00040000) +#define PSB_2D_PAT_1555ARGB (0x00048000) +#define PSB_2D_PAT_565RGB (0x00050000) +#define PSB_2D_PAT_0888ARGB (0x00058000) +#define PSB_2D_PAT_8888ARGB (0x00060000) + +#define PSB_2D_PAT_STRIDE_MASK (0x00007FFF) +#define PSB_2D_PAT_STRIDE_CLRMASK (0xFFFF8000) +#define PSB_2D_PAT_STRIDE_SHIFT (0) +/* + * WORD 1 - Base Address + */ +#define PSB_2D_PAT_ADDR_MASK (0x0FFFFFFC) +#define PSB_2D_PAT_ADDR_CLRMASK (0x00000003) +#define PSB_2D_PAT_ADDR_SHIFT (2) +#define PSB_2D_PAT_ADDR_ALIGNSHIFT (2) + +/* + * Destination Surface (PSB_2D_DST_SURF_BH) + */ +/* + * WORD 0 + */ + +#define PSB_2D_DST_FORMAT_MASK (0x00078000) +#define PSB_2D_DST_332RGB (0x00030000) +#define PSB_2D_DST_4444ARGB (0x00038000) +#define PSB_2D_DST_555RGB (0x00040000) +#define PSB_2D_DST_1555ARGB (0x00048000) +#define PSB_2D_DST_565RGB (0x00050000) +#define PSB_2D_DST_0888ARGB (0x00058000) +#define PSB_2D_DST_8888ARGB (0x00060000) +#define PSB_2D_DST_8888AYUV (0x00070000) + +#define PSB_2D_DST_STRIDE_MASK (0x00007FFF) +#define PSB_2D_DST_STRIDE_CLRMASK (0xFFFF8000) +#define PSB_2D_DST_STRIDE_SHIFT (0) +/* + * WORD 1 - Base Address + */ +#define PSB_2D_DST_ADDR_MASK (0x0FFFFFFC) +#define PSB_2D_DST_ADDR_CLRMASK (0x00000003) +#define PSB_2D_DST_ADDR_SHIFT (2) +#define PSB_2D_DST_ADDR_ALIGNSHIFT (2) + +/* + * Mask Surface (PSB_2D_MASK_SURF_BH) + */ +/* + * WORD 0 + */ +#define PSB_2D_MASK_STRIDE_MASK (0x00007FFF) +#define PSB_2D_MASK_STRIDE_CLRMASK (0xFFFF8000) +#define PSB_2D_MASK_STRIDE_SHIFT (0) +/* + * WORD 1 - Base Address + */ +#define PSB_2D_MASK_ADDR_MASK (0x0FFFFFFC) +#define PSB_2D_MASK_ADDR_CLRMASK (0x00000003) +#define PSB_2D_MASK_ADDR_SHIFT (2) +#define PSB_2D_MASK_ADDR_ALIGNSHIFT (2) + +/* + * Source Palette (PSB_2D_SRC_PAL_BH) + */ + +#define PSB_2D_SRCPAL_ADDR_SHIFT (0) +#define PSB_2D_SRCPAL_ADDR_CLRMASK (0xF0000007) +#define PSB_2D_SRCPAL_ADDR_MASK (0x0FFFFFF8) +#define PSB_2D_SRCPAL_BYTEALIGN (1024) + +/* + * Pattern Palette (PSB_2D_PAT_PAL_BH) + */ + +#define PSB_2D_PATPAL_ADDR_SHIFT (0) +#define PSB_2D_PATPAL_ADDR_CLRMASK (0xF0000007) +#define PSB_2D_PATPAL_ADDR_MASK (0x0FFFFFF8) +#define PSB_2D_PATPAL_BYTEALIGN (1024) + +/* + * Rop3 Codes (2 LS bytes) + */ + +#define PSB_2D_ROP3_SRCCOPY (0xCCCC) +#define PSB_2D_ROP3_PATCOPY (0xF0F0) +#define PSB_2D_ROP3_WHITENESS (0xFFFF) +#define PSB_2D_ROP3_BLACKNESS (0x0000) +#define PSB_2D_ROP3_SRC (0xCC) +#define PSB_2D_ROP3_PAT (0xF0) +#define PSB_2D_ROP3_DST (0xAA) + + +/* + * Sizes. + */ + +#define PSB_SCENE_HW_COOKIE_SIZE 16 +#define PSB_TA_MEM_HW_COOKIE_SIZE 16 + +/* + * Scene stuff. + */ + +#define PSB_NUM_HW_SCENES 2 + +/* + * Scheduler completion actions. + */ + +#define PSB_RASTER_BLOCK 0 +#define PSB_RASTER 1 +#define PSB_RETURN 2 +#define PSB_TA 3 + + +/*Power management*/ +#define PSB_PUNIT_PORT 0x04 +#define PSB_OSPMBA 0x78 +#define PSB_APMBA 0x7a +#define PSB_APM_CMD 0x0 +#define PSB_APM_STS 0x04 +#define PSB_PWRGT_VID_ENC_MASK 0x30 +#define PSB_PWRGT_VID_DEC_MASK 0xc +#define PSB_PWRGT_GL3_MASK 0xc0 + +#define PSB_PM_SSC 0x20 +#define PSB_PM_SSS 0x30 +#define PSB_PWRGT_DISPLAY_MASK 0xc /*on a different BA than video/gfx*/ +#define MDFLD_PWRGT_DISPLAY_A_CNTR 0x0000000c +#define MDFLD_PWRGT_DISPLAY_B_CNTR 0x0000c000 +#define MDFLD_PWRGT_DISPLAY_C_CNTR 0x00030000 +#define MDFLD_PWRGT_DISP_MIPI_CNTR 0x000c0000 +#define MDFLD_PWRGT_DISPLAY_CNTR (MDFLD_PWRGT_DISPLAY_A_CNTR | MDFLD_PWRGT_DISPLAY_B_CNTR | MDFLD_PWRGT_DISPLAY_C_CNTR | MDFLD_PWRGT_DISP_MIPI_CNTR)// 0x000fc00c +// Display SSS register bits are different in A0 vs. B0 +#define PSB_PWRGT_ISP_MASK 0xc00 +#define PSB_PWRGT_GFX_MASK 0x3 +#define MDFLD_PWRGT_DISPLAY_A_STS 0x000000c0 +#define MDFLD_PWRGT_DISPLAY_B_STS 0x00000300 +#define MDFLD_PWRGT_DISPLAY_C_STS 0x00000c00 +#define MDFLD_PWRGT_DISPLAY_A_STS_B0 0x0000000c +#define MDFLD_PWRGT_DISPLAY_B_STS_B0 0x0000c000 +#define MDFLD_PWRGT_DISPLAY_C_STS_B0 0x00030000 +#define MDFLD_PWRGT_DISP_MIPI_STS 0x000c0000 +#define MDFLD_PWRGT_DISPLAY_STS_A0 (MDFLD_PWRGT_DISPLAY_A_STS | MDFLD_PWRGT_DISPLAY_B_STS | MDFLD_PWRGT_DISPLAY_C_STS | MDFLD_PWRGT_DISP_MIPI_STS)// 0x000fc00c +#define MDFLD_PWRGT_DISPLAY_STS_B0 (MDFLD_PWRGT_DISPLAY_A_STS_B0 | MDFLD_PWRGT_DISPLAY_B_STS_B0 | MDFLD_PWRGT_DISPLAY_C_STS_B0 | MDFLD_PWRGT_DISP_MIPI_STS)// 0x000fc00c +#endif diff --git a/psb_ttm_fence_user.h b/psb_ttm_fence_user.h new file mode 100644 index 0000000..fc13f89 --- /dev/null +++ b/psb_ttm_fence_user.h @@ -0,0 +1,140 @@ +/************************************************************************** + * + * Copyright 2006-2008 Tungsten Graphics, Inc., Cedar Park, TX., USA + * All Rights Reserved. + * Copyright (c) 2009 VMware, Inc., Palo Alto, CA., USA + * All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * + **************************************************************************/ +/* + * Authors + * Thomas Hellström <thomas-at-tungstengraphics-dot-com> + */ + +#ifndef TTM_FENCE_USER_H +#define TTM_FENCE_USER_H + +#if !defined(__KERNEL__) && !defined(_KERNEL) +#include <stdint.h> +#endif + +#define TTM_FENCE_MAJOR 0 +#define TTM_FENCE_MINOR 1 +#define TTM_FENCE_PL 0 +#define TTM_FENCE_DATE "080819" + +/** + * struct ttm_fence_signaled_req + * + * @handle: Handle to the fence object. Input. + * + * @fence_type: Fence types we want to flush. Input. + * + * @flush: Boolean. Flush the indicated fence_types. Input. + * + * Argument to the TTM_FENCE_SIGNALED ioctl. + */ + +struct ttm_fence_signaled_req { + uint32_t handle; + uint32_t fence_type; + int32_t flush; + uint32_t pad64; +}; + +/** + * struct ttm_fence_rep + * + * @signaled_types: Fence type that has signaled. + * + * @fence_error: Command execution error. + * Hardware errors that are consequences of the execution + * of the command stream preceding the fence are reported + * here. + * + * Output argument to the TTM_FENCE_SIGNALED and + * TTM_FENCE_FINISH ioctls. + */ + +struct ttm_fence_rep { + uint32_t signaled_types; + uint32_t fence_error; +}; + +union ttm_fence_signaled_arg { + struct ttm_fence_signaled_req req; + struct ttm_fence_rep rep; +}; + +/* + * Waiting mode flags for the TTM_FENCE_FINISH ioctl. + * + * TTM_FENCE_FINISH_MODE_LAZY: Allow for sleeps during polling + * wait. + * + * TTM_FENCE_FINISH_MODE_NO_BLOCK: Don't block waiting for GPU, + * but return -EBUSY if the buffer is busy. + */ + +#define TTM_FENCE_FINISH_MODE_LAZY (1 << 0) +#define TTM_FENCE_FINISH_MODE_NO_BLOCK (1 << 1) + +/** + * struct ttm_fence_finish_req + * + * @handle: Handle to the fence object. Input. + * + * @fence_type: Fence types we want to finish. + * + * @mode: Wait mode. + * + * Input to the TTM_FENCE_FINISH ioctl. + */ + +struct ttm_fence_finish_req { + uint32_t handle; + uint32_t fence_type; + uint32_t mode; + uint32_t pad64; +}; + +union ttm_fence_finish_arg { + struct ttm_fence_finish_req req; + struct ttm_fence_rep rep; +}; + +/** + * struct ttm_fence_unref_arg + * + * @handle: Handle to the fence object. + * + * Argument to the TTM_FENCE_UNREF ioctl. + */ + +struct ttm_fence_unref_arg { + uint32_t handle; + uint32_t pad64; +}; + +/* + * Ioctl offsets frome extenstion start. + */ + +#define TTM_FENCE_SIGNALED 0x01 +#define TTM_FENCE_FINISH 0x02 +#define TTM_FENCE_UNREF 0x03 + +#endif diff --git a/psb_ttm_placement_user.h b/psb_ttm_placement_user.h new file mode 100644 index 0000000..84c1e79 --- /dev/null +++ b/psb_ttm_placement_user.h @@ -0,0 +1,273 @@ +/************************************************************************** + * + * Copyright 2006-2008 Tungsten Graphics, Inc., Cedar Park, TX., USA + * All Rights Reserved. + * Copyright (c) 2009 VMware, Inc., Palo Alto, CA., USA + * All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * + **************************************************************************/ +/* + * Authors + * Thomas Hellström <thomas-at-tungstengraphics-dot-com> + */ + +#ifndef _TTM_PLACEMENT_USER_H_ +#define _TTM_PLACEMENT_USER_H_ + +#if !defined(__KERNEL__) && !defined(_KERNEL) +#include <stdint.h> +#else +#include <linux/kernel.h> +#endif + +#include "ttm/ttm_placement.h" + +#define TTM_PLACEMENT_MAJOR 0 +#define TTM_PLACEMENT_MINOR 1 +#define TTM_PLACEMENT_PL 0 +#define TTM_PLACEMENT_DATE "080819" + +/** + * struct ttm_pl_create_req + * + * @size: The buffer object size. + * @placement: Flags that indicate initial acceptable + * placement. + * @page_alignment: Required alignment in pages. + * + * Input to the TTM_BO_CREATE ioctl. + */ + +struct ttm_pl_create_req { + uint64_t size; + uint32_t placement; + uint32_t page_alignment; +}; + +/** + * struct ttm_pl_create_ub_req + * + * @size: The buffer object size. + * @user_address: User-space address of the memory area that + * should be used to back the buffer object cast to 64-bit. + * @placement: Flags that indicate initial acceptable + * placement. + * @page_alignment: Required alignment in pages. + * + * Input to the TTM_BO_CREATE_UB ioctl. + */ + +struct ttm_pl_create_ub_req { + uint64_t size; + uint64_t user_address; + uint32_t placement; + uint32_t page_alignment; +}; + +/** + * struct ttm_pl_wrap_pvr_buf_req + * + * @handle: PVR buffer id + * @placement: Flags that indicate initial acceptable + * placement. + * + * Input to the TTM_WRAP_PVR_BUF ioctl. + */ +struct ttm_pl_wrap_pvr_buf_req { + uint32_t handle; + uint32_t placement; + uint32_t page_alignment; +}; + +/** + * struct ttm_pl_rep + * + * @gpu_offset: The current offset into the memory region used. + * This can be used directly by the GPU if there are no + * additional GPU mapping procedures used by the driver. + * + * @bo_size: Actual buffer object size. + * + * @map_handle: Offset into the device address space. + * Used for map, seek, read, write. This will never change + * during the lifetime of an object. + * + * @placement: Flag indicating the placement status of + * the buffer object using the TTM_PL flags above. + * + * @sync_object_arg: Used for user-space synchronization and + * depends on the synchronization model used. If fences are + * used, this is the buffer_object::fence_type_mask + * + * Output from the TTM_PL_CREATE and TTM_PL_REFERENCE, and + * TTM_PL_SETSTATUS ioctls. + */ + +struct ttm_pl_rep { + uint64_t gpu_offset; + uint64_t bo_size; + uint64_t map_handle; + uint32_t placement; + uint32_t handle; + uint32_t sync_object_arg; + uint32_t pad64; +}; + +/** + * struct ttm_pl_setstatus_req + * + * @set_placement: Placement flags to set. + * + * @clr_placement: Placement flags to clear. + * + * @handle: The object handle + * + * Input to the TTM_PL_SETSTATUS ioctl. + */ + +struct ttm_pl_setstatus_req { + uint32_t set_placement; + uint32_t clr_placement; + uint32_t handle; + uint32_t pad64; +}; + +/** + * struct ttm_pl_reference_req + * + * @handle: The object to put a reference on. + * + * Input to the TTM_PL_REFERENCE and the TTM_PL_UNREFERENCE ioctls. + */ + +struct ttm_pl_reference_req { + uint32_t handle; + uint32_t pad64; +}; + +/* + * ACCESS mode flags for SYNCCPU. + * + * TTM_SYNCCPU_MODE_READ will guarantee that the GPU is not + * writing to the buffer. + * + * TTM_SYNCCPU_MODE_WRITE will guarantee that the GPU is not + * accessing the buffer. + * + * TTM_SYNCCPU_MODE_NO_BLOCK makes sure the call does not wait + * for GPU accesses to finish but return -EBUSY. + * + * TTM_SYNCCPU_MODE_TRYCACHED Try to place the buffer in cacheable + * memory while synchronized for CPU. + */ + +#define TTM_PL_SYNCCPU_MODE_READ TTM_ACCESS_READ +#define TTM_PL_SYNCCPU_MODE_WRITE TTM_ACCESS_WRITE +#define TTM_PL_SYNCCPU_MODE_NO_BLOCK (1 << 2) +#define TTM_PL_SYNCCPU_MODE_TRYCACHED (1 << 3) + +/** + * struct ttm_pl_synccpu_arg + * + * @handle: The object to synchronize. + * + * @access_mode: access mode indicated by the + * TTM_SYNCCPU_MODE flags. + * + * @op: indicates whether to grab or release the + * buffer for cpu usage. + * + * Input to the TTM_PL_SYNCCPU ioctl. + */ + +struct ttm_pl_synccpu_arg { + uint32_t handle; + uint32_t access_mode; + enum { + TTM_PL_SYNCCPU_OP_GRAB, + TTM_PL_SYNCCPU_OP_RELEASE + } op; + uint32_t pad64; +}; + +/* + * Waiting mode flags for the TTM_BO_WAITIDLE ioctl. + * + * TTM_WAITIDLE_MODE_LAZY: Allow for sleeps during polling + * wait. + * + * TTM_WAITIDLE_MODE_NO_BLOCK: Don't block waiting for GPU, + * but return -EBUSY if the buffer is busy. + */ + +#define TTM_PL_WAITIDLE_MODE_LAZY (1 << 0) +#define TTM_PL_WAITIDLE_MODE_NO_BLOCK (1 << 1) + +/** + * struct ttm_waitidle_arg + * + * @handle: The object to synchronize. + * + * @mode: wait mode indicated by the + * TTM_SYNCCPU_MODE flags. + * + * Argument to the TTM_BO_WAITIDLE ioctl. + */ + +struct ttm_pl_waitidle_arg { + uint32_t handle; + uint32_t mode; +}; + +union ttm_pl_create_arg { + struct ttm_pl_create_req req; + struct ttm_pl_rep rep; +}; + +union ttm_pl_reference_arg { + struct ttm_pl_reference_req req; + struct ttm_pl_rep rep; +}; + +union ttm_pl_setstatus_arg { + struct ttm_pl_setstatus_req req; + struct ttm_pl_rep rep; +}; + +union ttm_pl_create_ub_arg { + struct ttm_pl_create_ub_req req; + struct ttm_pl_rep rep; +}; + +union ttm_pl_wrap_pvr_buf_arg { + struct ttm_pl_wrap_pvr_buf_req req; + struct ttm_pl_rep rep; +}; + +/* + * Ioctl offsets. + */ + +#define TTM_PL_CREATE 0x00 +#define TTM_PL_REFERENCE 0x01 +#define TTM_PL_UNREF 0x02 +#define TTM_PL_SYNCCPU 0x03 +#define TTM_PL_WAITIDLE 0x04 +#define TTM_PL_SETSTATUS 0x05 +#define TTM_PL_CREATE_UB 0x06 +#define TTM_PL_WRAP_PVR_BUF 0x07 + +#endif diff --git a/ttm_placement.h b/ttm_placement.h new file mode 100644 index 0000000..15a3ecb --- /dev/null +++ b/ttm_placement.h @@ -0,0 +1,102 @@ +/************************************************************************** + * + * Copyright (c) 2006-2009 VMware, Inc., Palo Alto, CA., USA + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + **************************************************************************/ +/* + * Authors: Thomas Hellstrom <thellstrom-at-vmware-dot-com> + */ + +#ifndef _TTM_PLACEMENT_H_ +#define _TTM_PLACEMENT_H_ +/* + * Memory regions for data placement. + */ + +#define TTM_PL_SYSTEM 0 +#define TTM_PL_TT 1 +#define TTM_PL_VRAM 2 +#define TTM_PL_PRIV0 3 +#define TTM_PL_PRIV1 4 +#define TTM_PL_PRIV2 5 +#define TTM_PL_PRIV3 6 +#define TTM_PL_PRIV4 7 +#define TTM_PL_PRIV5 8 +#define TTM_PL_SWAPPED 15 + +#define TTM_PL_FLAG_SYSTEM (1 << TTM_PL_SYSTEM) +#define TTM_PL_FLAG_TT (1 << TTM_PL_TT) +#define TTM_PL_FLAG_VRAM (1 << TTM_PL_VRAM) +#define TTM_PL_FLAG_PRIV0 (1 << TTM_PL_PRIV0) +#define TTM_PL_FLAG_PRIV1 (1 << TTM_PL_PRIV1) +#define TTM_PL_FLAG_PRIV2 (1 << TTM_PL_PRIV2) +#define TTM_PL_FLAG_PRIV3 (1 << TTM_PL_PRIV3) +#define TTM_PL_FLAG_PRIV4 (1 << TTM_PL_PRIV4) +#define TTM_PL_FLAG_PRIV5 (1 << TTM_PL_PRIV5) +#define TTM_PL_FLAG_SWAPPED (1 << TTM_PL_SWAPPED) +#define TTM_PL_MASK_MEM 0x0000FFFF + +/* + * Other flags that affects data placement. + * TTM_PL_FLAG_CACHED indicates cache-coherent mappings + * if available. + * TTM_PL_FLAG_SHARED means that another application may + * reference the buffer. + * TTM_PL_FLAG_NO_EVICT means that the buffer may never + * be evicted to make room for other buffers. + * TTM_PL_FLAG_NO_SWAP means that the buffer cannot be + * swapped. If NO_EVICT is not set the buffer can still + * be moved as long as its placement allows it. + */ + +#define TTM_PL_FLAG_CACHED (1 << 16) +#define TTM_PL_FLAG_UNCACHED (1 << 17) +#define TTM_PL_FLAG_WC (1 << 18) +#define TTM_PL_FLAG_SHARED (1 << 20) +#define TTM_PL_FLAG_NO_EVICT (1 << 21) +#define TTM_PL_FLAG_NO_SWAP (1 << 22) + +#define TTM_PL_MASK_CACHING (TTM_PL_FLAG_CACHED | \ + TTM_PL_FLAG_UNCACHED | \ + TTM_PL_FLAG_WC) + +#define TTM_PL_MASK_MEMTYPE (TTM_PL_MASK_MEM | TTM_PL_MASK_CACHING) + +/* + * Access flags to be used for CPU- and GPU- mappings. + * The idea is that the TTM synchronization mechanism will + * allow concurrent READ access and exclusive write access. + * Currently GPU- and CPU accesses are exclusive. + */ + +#define TTM_ACCESS_READ (1 << 0) +#define TTM_ACCESS_WRITE (1 << 1) + +/* + * TTM_PL_FLAG_VED indicates gralloc buffer allocation is active and + * that TTM allocation must be inhibited. + */ +#define TTM_PL_FLAG_VED (1 << 22) + +#endif |