platform/upstream/nasm - Domain: System / Toolchain;

Age	Commit message (Expand)	Author	Files	Lines
2013-08-16	AVX-512: Add EVEX encoding and new instructions	Jin Kyu Song	1	-9/+439
2013-07-21	insns: Fix MOVLPD	Cyrill Gorcunov	1	-2/+2
2013-07-21	insns: Fix MOVNTDQA instruction	Cyrill Gorcunov	1	-1/+1
2013-07-21	insns: Fix VMOVNTDQA instruction	Cyrill Gorcunov	1	-1/+1
2013-07-19	BR 3392260: Handle instructions only separated by vector SIB size	H. Peter Anvin	1	-19/+19
2013-06-30	insns: Fix vspllw instruction	MITSUNARI Shigeo	1	-1/+1
2013-06-01	insns: Fix vgatherqpd instruction	MITSUNARI Shigeo	1	-1/+1
2013-05-24	insns: Fix VPMOVSXBQ instruction	MITSUNARI Shigeo	1	-1/+1
2013-05-12	insns.dat: Add note about AMD TBM instructions	Cyrill Gorcunov	1	-1/+1
2013-05-12	insns.dat: Add BLCMSK	Cyrill Gorcunov	1	-0/+2
2013-05-12	insns.dat: Add BLCS	Cyrill Gorcunov	1	-0/+2
2013-05-12	insns.dat: Add BLSFILL	Cyrill Gorcunov	1	-0/+2
2013-05-12	insns.dat: Add BLCFILL	Cyrill Gorcunov	1	-0/+2
2013-05-12	insns.dat: Add BLCIC	Cyrill Gorcunov	1	-0/+2
2013-05-12	insns.dat: Add BLCI	Cyrill Gorcunov	1	-0/+2
2013-05-12	insns.dat: Add BLSIC	Cyrill Gorcunov	1	-0/+2
2013-05-12	insns.dat: Add immediate form of BEXTR	Cyrill Gorcunov	1	-0/+2
2013-05-12	insns.dat: Add T1MSKC intstruction	Cyrill Gorcunov	1	-1/+3
2013-05-12	insns.dat: Add TZMSK instruction	Cyrill Gorcunov	1	-0/+2
2013-05-12	insns.dat: Move TZCNT for alphabetical order	Cyrill Gorcunov	1	-3/+3
2013-05-04	insns.dat: Udate year	Cyrill Gorcunov	1	-1/+1
2013-05-04	br3392250: insns -- Allow byte size in PREFETCHTx instructions	Cyrill Gorcunov	1	-4/+4
2013-03-03	insns: Remove pushseg/popseg internal bytecodes	Ben Rudiak-Gould	1	-5/+11
2013-03-01	Remove +s	Ben Rudiak-Gould	1	-128/+173
2013-02-21	BR3392242: insns.dat -- Support AMD SVM instructions in 32bit mode	Andrew Nayenko	1	-7/+7
2013-02-20	Fix jmp/call near offsets in long mode	Ben Rudiak-Gould	1	-36/+37
2013-02-20	Add np and similar prefixes to instructions that should have them	Ben Rudiak-Gould	1	-56/+56
2012-10-08	BR 3327107: fix assembly of VPCMPGTQ	Marat Dukhan	1	-1/+1
2012-09-25	insns.dat: Mark the immediate for shift instructions as imm8	H. Peter Anvin	1	-32/+32
2012-09-25	BR 3392227: Remove SB flag from SHIFT rm,imm	H. Peter Anvin	1	-32/+32
2012-09-09	Add CLAC and STAC instructions from AVX spec 014 (319433-014)	H. Peter Anvin	1	-0/+4
2012-08-17	Add back the 256-bit form of the VORPD instruction	H. Peter Anvin	1	-0/+1
2012-07-28	BR 3392218: Disassemble 82h opcodes	H. Peter Anvin	1	-0/+8
2012-07-22	hle: opcode A2 forbidden with HLE prefixes	H. Peter Anvin	1	-1/+1
2012-07-20	isnsn.dat: add norexw to instructions with only 32- and 64-bit forms	H. Peter Anvin	1	-6/+6
2012-07-13	insns.dat: new instructions from the 013 AVX spec	H. Peter Anvin	1	-0/+9
2012-05-24	insns.dat: Add VPMOVMSKB reg32,ymmreg instruction	Cyrill Gorcunov	1	-0/+1
2012-03-06	BR3385573: insns: Fix VPMOVSXBW	Cyrill Gorcunov	1	-1/+1
2012-03-05	Try again to fix our handling of MOVD/MOVQ	H. Peter Anvin	1	-8/+8
2012-02-25	insns.dat: MOV is not lockable; CMPXCHG16B does not support HLE	H. Peter Anvin	1	-5/+5
2012-02-25	HLE: Change NOHLE to be an instruction flag	H. Peter Anvin	1	-4/+4
2012-02-25	Assume the undocumented CMPXCHG486 opcode was lockable	H. Peter Anvin	1	-3/+3
2012-02-26	insns.dat: Add IF_LOCK flag on appropriate instructions	Cyrill Gorcunov	1	-154/+154
2012-02-25	Clean up JMP/CALL patterns, especially for 64 bits	H. Peter Anvin	1	-8/+11
2012-02-26	insns.dat: Add nohle for MOV in case of moffset destination	Cyrill Gorcunov	1	-4/+4
2012-02-25	insns.dat: Add hlexr flag for MOV instruction	Cyrill Gorcunov	1	-12/+12
2012-02-25	insns.dat: Add hlenl flag for XCHG instruction	Cyrill Gorcunov	1	-8/+8
2012-02-25	insns.dat: Add hle flag for XADD instruction	Cyrill Gorcunov	1	-4/+4
2012-02-25	insns.dat: Add hle flag for XOR instruction	Cyrill Gorcunov	1	-14/+14
2012-02-25	insns.dat: Add hle flag for SUB instruction	Cyrill Gorcunov	1	-14/+14