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author | H. Peter Anvin <hpa@zytor.com> | 2007-12-10 15:35:28 -0800 |
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committer | H. Peter Anvin <hpa@zytor.com> | 2007-12-10 15:35:28 -0800 |
commit | e55c836b5af387054cfb921f2554a1bc8657d91f (patch) | |
tree | f5e627121d123a9c591e5f70f6851ec967b47af0 /misc | |
parent | 5f5a252a367974a04a576d7a988117aeb67c0b26 (diff) | |
download | nasm-e55c836b5af387054cfb921f2554a1bc8657d91f.tar.gz nasm-e55c836b5af387054cfb921f2554a1bc8657d91f.tar.bz2 nasm-e55c836b5af387054cfb921f2554a1bc8657d91f.zip |
Document naming of registers in 64-bit mode
Intel's docs diverge from AMD's docs (MASM follow AMD's docs);
formally document what we're doing and include a file of macros in
case someone wants to use alternate names.
Diffstat (limited to 'misc')
-rw-r--r-- | misc/altreg.inc | 67 |
1 files changed, 67 insertions, 0 deletions
diff --git a/misc/altreg.inc b/misc/altreg.inc new file mode 100644 index 0000000..91e86db --- /dev/null +++ b/misc/altreg.inc @@ -0,0 +1,67 @@ +;; +;; altreg.inc +;; +;; Alternate register names for 64-bit mode +;; + +;; +;; Intel documents R8L-R15L instead of R8B-R15B +;; (Warning: this may confuse people with an AT&T-style assembly +;; background, where "r8l" means R8D, etc.) +;; +%idefine r8l r8b +%idefine r9l r9b +%idefine r10l r10b +%idefine r11l r11b +%idefine r12l r12b +%idefine r13l r13b +%idefine r14l r14b +%idefine r15l r15b + +;; +;; Numeric register names for the lower 8 registers +;; +%idefine r0 rax +%idefine r1 rcx +%idefine r2 rdx +%idefine r3 rbx +%idefine r4 rsp +%idefine r5 rbp +%idefine r6 rsi +%idefine r7 rdi + +%idefine r0d eax +%idefine r1d ecx +%idefine r2d edx +%idefine r3d ebx +%idefine r4d esp +%idefine r5d ebp +%idefine r6d esi +%idefine r7d edi + +%idefine r0w ax +%idefine r1w cx +%idefine r2w dx +%idefine r3w bx +%idefine r4w sp +%idefine r5w bp +%idefine r6w si +%idefine r7w di + +%idefine r0b al +%idefine r1b cl +%idefine r2b dl +%idefine r3b bl +%idefine r4b spl +%idefine r5b bpl +%idefine r6b sil +%idefine r7b dil + +%idefine r0l al +%idefine r1l cl +%idefine r2l dl +%idefine r3l bl +%idefine r4l spl +%idefine r5l bpl +%idefine r6l sil +%idefine r7l dil |